Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Denshi Kabushiki Kaisha

Hitachi Microcomputer System, Ltd.

Masaharu Kubo

Iwao Takemoto

Shinya Ohba

Norio Koike

Masashi Horiguchi

Masakazu Aoki

Haruhisa Ando

Asao Nishimura

Kazuyoshi Shiba

Toshiaki Masuhara

Toshio Miyamoto

Koki Noguchi

Satoshi Michishita

Ryoichi Hori

Masaaki Nakai

Shusaku Nagahara

Shoji Hanamura

Norikazu Hashimoto

Shuhei Tanaka

Osamu Kubo

Kiyoo Itoh

Hideo Miura

Kouki Noguchi

Ryo Fujita

Osamu Minato

Tohru Nakamura

Minoru Nagata

Tetsuya Hayashida

Shigeru Nishimatsu

Yasuhiko Takahashi

Kazuhiko Sagara

Kazuo Nakazato

Michihiro Mishima

Ryuichi Izawa

Motoaki Matsumoto

Kazuhiko Kajigaya

Takayuki Kawahara

Yoshinobu Nakagome

Nobuyoshi Matsuura

Nozomu Matsuzaki

Satoshi Meguro

Toshio Sasaki

Yoshio Sakai

Toshihisa Tsukada

Toshiyuki Akiyama

Toru Baji

Eiichi Maruyama

Kenji Takahashi

Noriyuki Homma

Toshifumi Ozaki

Terumi Sawase

Yasunobu Kosa

Tokumasa Yasui

Yasuhiko Kouno

Hiroyuki Mizuno

Toshihiko Tanaka

Akira Nagai

Norio Suzuki

Kazuhiro Sato

Mitsuru Hiraki

Takuya Imaide

Kazuyuki Miyazawa

Masataka Kato

Katsuhiro Shimohigashi

Hideaki Yamamoto

Akira Sasano

Susumu Narita

Koichi Seki

Ichiro Anjo

Tadaaki Hirai

Ikuya Kawasaki

Takashi Hattori

Hideo Sunami

Yukio Takasaki

Hiromi Abe

Yoshinori Imamura

Hitoshi Akamine

Atsuyoshi Koike

Masatada Horiuchi

Tetsuro Matsumoto

Hiroo Masuda

Hiroshi Otori

Katsuki Miyauchi

Kotaro Nishimura

Ryuji Shibata

Saburo Ataka

Fumiyuki Kanai

Noriyuki Honma

Akihide Okuda

Satoshi Takase

Hideo Inayoshi

Mitsuyoshi Yamamoto

Toshiya Uenishi

Akira Uchiyama

Keikichi Moriwaki

Norio Kokie

Joh Nakajima

Syoji Hanamura

Yataro Yamashita

Syuji Ikeda

An electronic circuit device has a high-density mount board (), on which are disposed a microcomputer () and random access memory () which are connected to each other through an exclusive memory bus () for high-speed data transfer, a programmable device () which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory () which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Electronic circuit device

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Semiconductor device

An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

A wiring substrate is manufactured in short TAT. Wirings of the wiring substrate are formed by an exposure treatment using a photomask which has shade patterns each containing at least nano particles and a binder.

Wiring substrate manufacturing method

In a MOS circuit comprising a plurality of MOSFETs constituting a digital circuit, an input signal is supplied to the digital circuit, and a first back bias voltage is supplied to a semiconductor substrate or a semiconductor well region in which the MOSFETs are formed, so that a pn junction between the semiconductor substrate or the semiconductor well region and a source region is brought to a forward voltage. In a non-operating state in which a circuit operation is suspended by the input signal supplied to the digital circuit as a fixed level, a second back bias voltage is applied to the semiconductor substrate or the semiconductor well region so that the pn junction between the semiconductor substrate or the semiconductor well region and the source region is brought to a reverse voltage.

Method of setting back bias of MOS circuit, and MOS integrated circuit

CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring () to a third-layer () formed on a main surface of a silicon substrate (), and as another part, a fourth-layer wiring () to a seventh-layer wiring () formed on a main surface of a glass substrate () different from the silicon substrate (). The main surface of the silicon substrate () and the main surface of the glass substrate () are arranged in face-to-face relation with each other, and a plurality of microbumps (A) formed at the uppermost portion of the silicon substrate () and a plurality of microbumps (B) formed at the uppermost portion of the glass substrate () are electrically connected, thereby constituting the CMOS logic LSI as a whole.

Integrated circuit device having reduced substrate size and a method for manufacturing the same

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS, WHEREIN ELECTRODES OF THE SEMICONDUCTOR CHIPS ARE ELECTRICALLY CONNECTED TOGETHER VIA WIRING SUBSTRATES OF THE SEMICONDUCTOR CHIPS

A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

To suppress oxidation of the inner walls of element isolation grooves otherwise occurring during thermal oxidation processes, a nitrogen introducing layer, that has a lower diffusion coefficient relative to an oxidizing agent, is formed at the surface portion of a silicon oxide film buried within an element isolation groove. This nitrogen introduced layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or the like) in vapor phase from diffusing into the silicon oxide film during thermal processing steps. The nitrogen introduced layer is formed by performing nitrogen ion implantation into the entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen that has been doped.

Semiconductor integrated circuit device and method of fabricating the same

The present invention provides a semiconductor device and a manufacturing method thereof which can realize fine processing while preventing a warp of a semiconductor wafer. In forming a plurality of semiconductor elements on a semiconductor wafer, grooves for attenuating stress are formed in scribe regions defined between semiconductor element forming regions. Here, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain in the scribe regions. On the alignment pattern forming regions of the scribe regions, an alignment pattern or a TEG pattern which is used in a photolithography step is formed.

Method for forming grooves in the scribe region to prevent a warp of a semiconductor substrate

Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.

Semiconductor wafer and manufacturing method of semiconductor device

Growing community of inventors

Hachioji, Japan

Masaharu Kubo