Halo Lsi, Inc.

Halo, Inc.

Masaharu Kirihara

Tomoko Ogura

A bit line decoding circuit for accessing an array of two-bit memory cells. Two adjacent memory cells can be accessed by applying appropriate voltages to the terminals of the cells. A bit line decoder selects plural bit lines in the memory array and provides paths to apply or receive the voltages to or from the selected bit lines. In one embodiment, shared control gates of pass transistors which function as the bit line selection in a bit line deocder provides reduction in the number of control signals. Functions of applying a voltage for neighbor effect reduction and of providing a path for a reference voltage are also implemented in further embodiments.

Decoder circuit with function of plural series bit line selection

According to the present invention, a voltage level shifter with smaller size and less latch-up probability is described, in which extra two N-MOS transistors and two P-MOS transistors are added. The extra transistors help node voltages increase or decrease appropriately, and then the size of driving transistors can be small. As a result, the total size of the layout can be smaller. In addition, the voltage increasing or decreasing done by the extra transistors reduce a voltage bouncing which call cause latch-up.

High voltage level shifter

A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment, a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.

Growing community of inventors

Beacon, NY, United States of America

Masaharu Kirihara