Hitachi, Ltd.

Renesas Electronics Corporation

Masaharu Kinoshita

Yoshitaka Sasago

Takashi Kobayashi

Norikatsu Takaura

Akio Shima

Satoru Hanzawa

Mitsuharu Tai

Takahiro Morikawa

Kenzo Kurotsuchi

Motoyasu Terao

Toshiyuki Mine

Hiroyuki Minemura

Tomonori Sekiguchi

Keiji Watanabe

Hitoshi Kume

Minoru Ogushi

Nozomu Matsuzaki

Yoshinobu Kimura

Hideyuki Matsuoka

Noriyuki Sakuma

Nobuyuki Sugii

Shuntaro Machida

Toshimichi Shintani

Akira Kotabe

Atsushi Isobe

Tadanobu Toba

Yoshihisa Fujisaki

Yuichi Matsui

Daisuke Ryuzaki

Kazuo Ono

Kenichi Shimbo

Tetsufumi Kawamura

Kenichi Akita

Masatoshi Morishita

Koji Fujisaki

Yoshitska Sasago

Takasumi Oyanagi

Masahito Kitamura

Norikastsu Takaura

A data processing method is performed by an edge device acquiring collected data from a collection target and a first computer capable of communicating with the edge device. The method includes: a first calculation process of, by the edge device, storing the collected data in a secure region to which referring of internally stored information from outside is not allowable and calculating first data which has a data amount less than the collected data and is irreversible in the secure region based on the stored collected data; a first communication process of, by the edge device, transmitting the first data calculated through the first calculation process to the first computer; and a second calculation process of, by the first computer, calculating second data based on the first data transmitted from the edge device through the first communication process.

Data processing method, edge device, and data processing system

A redeposited material is removed so as to electrically observe a microelement without causing foreign matters or metal contamination. An FIB device (charged particle beam device) includes an FIB barrel which discharges the focused ion beam (charged particle beam), a stage which holds a sample (substrate), a microcurrent measuring device (current measuring unit) which measures a leakage current from the sample, and a timer (time measuring unit) which measures a time to emit the focused ion beam and a time to measure the leakage current. Further, the FIB device includes a system control unit (control unit) which synchronizes a time to emit the focused ion beam and a time to measure the leakage current by the microcurrent measuring device.

Sensor characteristic evaluation method and charged particle beam device

A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.

Manufacturing device, system and method for outputting a manufacturing process flow having the shortest total process time among a plurality of manufacturing process flows

A manufacturing method of a MEMS sensor includes a step of, by irradiating a first hole formed in a second layer on a semiconductor substrate with a focused ion beam for a first predetermined time, forming a first sealing film, which seals the first hole, on the first hole, and a step of, by irradiating a second hole formed in the second layer with a focused ion beam for a second predetermined time, forming a second sealing film, which seals the second hole, on the second hole. At this time, each of the first predetermined time and the second predetermined time is a time in which thermal equilibrium of the second layer is maintainable, and the step of forming the first sealing film and the step of forming the second sealing film are performed repeatedly.

Manufacturing method of MEMS sensor

When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Nonvolatile memory device and method for manufacturing same

Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line () which is provided above the substrate; a first laminated body, which is disposed above the first word line (), and which has the N+1 (N&#x2267;1) number of first inter-gate insulating layers (-) and the N number of first semiconductor layers (-) alternately laminated in the height direction of the substrate; a first bit line (), which extends in the direction that intersects the first word line (), and which is disposed above the laminated body; a first gate insulating layer () which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (-) and those of the N number of the first semiconductor layers (-); a first channel layer () which is provided on the side surface of the first gate insulating layer (); and a first variable resistance material layer () which is provided on the side surface of the first channel layer. The first variable material layer () is in a region where the first word line () and the first bit line () intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

Semiconductor storage device and method for manufacturing same

A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (and) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer () interposed, and a resistance-change material layer () is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.

Semiconductor storage device and method of fabricating same

A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Non-volatile memory device and production method thereof

With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines () and bit lines () are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.

Semiconductor storage device

In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

Nonvolatile semiconductor memory device and manufacturing method thereof

A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of SbTeand GeTe. The phase change memory layer having the superlattice structure includes a SbTelayer containing Zr in contact with the first electrode.

Superlattice phase change memory including Sb2Te3 layers containing Zr

Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.

Growing community of inventors

Kokubunji, Japan

Masaharu Kinoshita