Fujitsu Corporation

Masaharu Kimura

Koichi Kuroiwa

Hideyuki Iino

Hiroyuki Fujiyama

Shinichi Utsunomiya

Noriko Kadomaru

Makoto Miyagawa

Kenji Shirasawa

Shoji Matsushita

Yoshihiro Tada

A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.

Data processing system, memory access device and method including

An apparatus for effecting a logic circuit simulation based on logic circuit information concerning the logic circuit and input signal information concerning each of circuit elements constituting the logic circuit according to simulation control information and producing output signal information, and a method for producing a semiconductor device using the simulation approach. By determining an input side signal delay value and an output side signal delay value with respect to a circuit element which is a simulation object, comparing the determined delay values and, based on a result of the comparing, determining an output signal value of the simulation object circuit element, it is possible to effect a perfect simulation on a transistor level subordinate to a gate level in practical processing time without using a special computer.

Apparatus for effecting simulation of a logic circuit and method for

A semiconductor integrated circuit device includes an external terminal, an internal logic circuit, and an input/output interface circuit. The input/output interface circuit includes an input circuit, a selection circuit and an output circuit. The input circuit receives an input signal and supplies the internal logic circuit with the same. The selection circuit selects either the input signal supplied from the input circuit or an output signal supplied from the internal logic circuit. The output circuit outputs the selected one of the input signal and output signal to the external terminal. A loop circuit is formed by the input circuit, selection circuit and output circuit. The loop circuit logically includes an odd number of inverters.

Semiconductor integrated circuit device having improved input/output

Growing community of inventors

Kawasaki, Japan

Masaharu Kimura