Fujitsu Corporation

Fujitsu Vlsi Limited

Masaharu Kagohashi

Akihiro Iwase

Teruo Seki

A semiconductor memory device includes a sense amplifier and a load circuit which are connected to a pair of data buses through which cell data is read. The sense amplifier produces an output data signal in accordance with voltage potentials of transfer signals on the data buses. During data reading operation of the memory device, the sense amplifier is enabled and the transfer signals on the data buses have a different voltage potential level from each other. The load circuit sets the data buses at a predetermined reset voltage potential in a stand by state of the data reading operation. The reset voltage potential is intermediate of the voltage potential levels of the data buses when the sense amplifier is enabled.

Data outputting circuit for semiconductor memory device

A load generator is disclosed, which controls the voltage swing of the complementary logic signals generated in a semiconductor memory device. The load generator includes a first load circuit for controlling the potential levels of the signals appearing on a pair of complementary input signal lines. The first load circuit includes a first and second voltage dividers connected to the complementary input signal lines. Each of the first and second voltage dividers include a first voltage dividing transistor and a first voltage dividing resistive element connected in series between the semiconductor's low and high potential power supplies. The two first voltage dividing transistors are connected to each other in such a manner that a voltage, divided by one of the two transistors, is applied to the gate of the other transistor. The load generator further includes a second load circuit for controlling the potential levels of the signals appearing on a pair of complementary output signal lines. The second load circuit includes a third and fourth voltage dividing circuits associated with the first and second voltage dividing circuits and connected to the complementary output signal lines, respectively. Each of the third and fourth voltage dividing circuits includes a second voltage dividing transistor and a second voltage dividing resistive element, connected in series between the low and high potential power supplies.

Growing community of inventors

Kasugai, Japan

Masaharu Kagohashi