Keysight Technologies, Inc.

Hewlett-Packard Company

Agilent Technologies, Inc.

Masaharu Goto

Naoki Kobayashi

Christopher Koerner

Kiyoshi Chikamatsu

Katsuhito Iwasaki

Masaru Shimura

Kenichi Ito

Andrew Robert Lehane

James Oliver Barnes

Hideo Akama

Nobuyuki Kasuga

Koji Tokuno

Takuya Otani

Norio Sone

Alberto Gutierrez, Jr

Tomonori Ura

Minoru Uchida

Ken Yawata

Ian Reading

Koh Murata

Tomoya Fujisaki

A method is provided for finding events that predict failure of an electronic component of a data processing system. The method includes extracting EDSs from a data stream including an output of the electronic component as a function of time, each EDS satisfying an extraction protocol and being characterized by a time stamp indicating a time at which the EDS was present; transforming the EDSs to corresponding CSVs; clustering the CSVs into clusters, each cluster being characterized by a number of CSVs in the cluster and a range of time stamps for the CSVs in the cluster, where the clustering is determined by a similarity protocol; and identifying a predictor cluster from the clusters having CSVs with time stamps during a period that is nearer a point of failure of the electronic component than other clusters having CSVs, where the predictor cluster has more than a predetermined number of CSVs.

Method and apparatus for predicting failure of a component

A method of analyzing measurement data includes sorting EDSs into similarity clusters including a representative RDS; labeling the similarity clusters; sorting the EDSs or RDSs into sub-clusters; selecting one of the EDSs or RDSs in each of the sub-clusters as a search seed representative of the sub-cluster; sorting measurement EDSs from measurement data into measurement clusters including a representative measurement RDS; determining for each search seed a most similar one of the measurement EDSs or RDSs; identifying the determined most similar one of the measurement EDSs or RDSs for each search seed as a classification segment corresponding to the search seed; sorting new measurement EDSs or RDSs into classification clusters with the classification segments; classifying all the new measurement EDSs or RDSs in each classification cluster the same as the corresponding classification segment; and determining whether patterns of interest are in the measurement data stream based on the classification clusters.

Method and system for recording and analyzing large amounts of data

A system for detecting changes in an electronic component and a method for operating a data processing system for finding events that predict an electronic component's failure are disclosed. The system includes an input port that receives a data stream that includes an ordered sequence of data values generated by the electronic component. A controller identifies a segment of the data stream (EDS), transforms the EDS to a CSV, and compares the CSV to a plurality of reference signature vectors (RSVs) to determine if the CSV is similar to any of the RSVs. Information identifying a new CSV is stored in an RSV database if the new CSV is similar to one of the RSVs, and a new RSV is created if the new CSV is not similar to any of the RSVs in said RSV database. A predictor RSV that occurs as the electronic component ages is identified.

A system for recording and analyzing a data stream, a method for analyzing a data stream, and a computer readable memory that stores instructions that cause a computer to execute a method of analyzing a data stream are disclosed. The system includes an input port, output port, buffer, and controller. The controller identifies a segment, referred to as a new extracted data segment (EDS) of the data stream stored in a buffer, the new EDS satisfying an extraction protocol. The controller compares the new EDS to each of a plurality of reference data segments (RDSs) using a similarity protocol. A new RDS is created if the new EDS is not similar to an existing EDS. If the new EDS is similar to an RDS, the RDS is updated to list that new EDS as being similar.

Data recording and analysis system

A method for operating a data processing system and computer readable medium causing a data processing system to execute that method are disclosed. The method includes causing the data processing system to receive a plurality of first EDSs classified into a plurality of first clusters and a first RDS for each of the plurality of first clusters and displaying, a first display for each of the first clusters and a RDS for each of the first clusters. The data processing system receives information from a user specifying one or more of the first clusters to be further clustered to arrive at a specified number of second clusters into which the specified one or more first clusters are to be classified, and performing a second clustering on the selected clusters. The method also includes displaying a second display that includes a plurality of second EDSs, classified into the second clusters.

Apparatus and method for interactively viewing and clustering data segments from long data recordings

An apparatus and a method for using a signal analyzer are disclosed. The apparatus includes an input port having a first plurality of input channels. The input port generates a digital data stream from each of the first plurality of input channels. The apparatus also includes a trigger bank having a second plurality of trigger processors, each trigger processor receiving a digital data stream chosen from the digital data streams and generating a trigger output having one of a plurality of possible values from the digital data stream. A trigger combiner that receives each of the trigger outputs and generates a trigger signal if the combined trigger outputs satisfy a predetermined criterion. A controller copies the digital data streams to a memory and copies the trigger processor outputs to the memory in response to the trigger combiner generating the trigger signal.

Multi-channel triggering apparatus and method

A test system measures parameters of a device under test (DUT), including a transistor. The test system includes a first voltage source unit for supplying a gate voltage; a second voltage source unit for supplying one of a drain voltage or a source voltage, the second voltage source having a current measurement device for detecting one of a drain current or a source current flowing through the transistor, respectively; a feedback unit for outputting a feedback current, based on the one of the drain or source currents; and an error amplifier for outputting a feedback control signal, based on comparison of the feedback current and a target current value. The first voltage source unit adjusts the gate voltage based on the feedback control signal so that the one of the drain or source currents converges to match the target current value.

System and method for converging current with target current in device under test

The apparatus includes a frame to accommodate more than two instrumentation modules; a multiplexed bus associated with the frame and including more than two connectors; and a sense instrumentation module and a source instrumentation module mounted in the frame, electrically connected to respective ones of the connectors, and collectively including a communication link, and a circuit path that includes, in series between a sense input and a source output, a sense circuit to generate a sense output signal representing a sensed parameter dependent on a source signal; a feedback controller to generate a control signal in response to the sense output signal; and a source circuit to generate the source signal in response to the control signal. The communication link is in the circuit path, and includes a bus transmitter and a bus receiver each configured to select a channel of the multiplexed bus via which to communicate.

Apparatus having feedback loops between multiple pairs of instrumentation modules

A print circuit board includes: a first surface; a guard plane disposed on an inner layer; a high insulated region formed on the first surface of the board so as to be opposed to the guard plane, the high insulated region being substantially surrounded by one or more first guard patterns; and a quasi-high insulated region formed on the first surface of the board so as to be disposed adjacent to the high insulated region. The quasi-high insulated region is substantially surrounded by at least a part of the one or more first guard patterns and by one or more second guard patterns, in which the one or more first guard patterns and the one or more second guard patterns are each formed by forming one or more trenches in the first surface of the board so as to expose the guard plane on a bottom surface of the trenches.

Print circuit board with high insulated region, method of manufacturing thereof, and print circuit board assembly thereof

A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.

Method for optimizing a pattern generation program, a program, and a signal generator

A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.

Current/charge-voltage converter

The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage levels. The invention also offers a method used for the calibration. The apparatus is equipped with a plurality of units (timing vector generators) each having a timing-generating circuit (a capture timing generator) and an external common reference timing circuit (a golden edge generator) outside the units. Each unit comprises: (1) a timing comparator circuit (a capture comparator) for comparing the timing each of the timing-generating circuits with the timing of the reference timing circuit to determine whether the former timing leads or lags the latter timing; and (2) a counter circuit which counts a number of comparisons made by the comparator circuit until their sequential relation has been reversed.

Apparatus for testing and measuring electronic device and method of

A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements. When the active edge has arrived at each of the selection gates, each is held in an output state until the input to the selection gates becomes inactive, even if the selection signals changes.

Timing adjustment circuit

A system and method for compensating in real time the dynamic power variation of a computer chip containing CMOS devices is provided. The present invention functions to control the temperature variations on the chip thus eliminating the drift to analog signals associated with CMOS devices. The present invention controls the temperature with the use of a compensation heater located on the CMOS chip. The compensation heater is driven by a plurality of signals which act in harmony with one another to control the temperature on the chip when it becomes unstable. The system and method includes driving the compensation heater with a maximum dynamic power value to effectively maintain the temperature on the chip, evaluating the chip for temperature fluctuation, and compensating for the temperature fluctuation by driving the compensation heater with at least one compensation power value.

System and method for dynamic power compensation

A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.

Growing community of inventors

Hanno, Japan

Masaharu Goto