Texas Instruments Corporation

Victor Company of Japan, Limited

Masafumi Yugami

Kazuhiro Ohara

Yasuo Satoh

Makiko Suzuki

A transmission system omits blanking signals from vertical and horizontal synchronizing signals for video data while securing synchronized transmission between a transmission side and a reception side. To achieve this, the transmission system transmits first synchronizing data (HV) for identifying vertical synchronization, second synchronizing data (HDp) for identifying and synchronizing an effective video line, pixel data for the effective video line, a required digital audio signal, and auxiliary control data. The transmission system can reduce a transmission capacity, optimize a transmission format for optical wireless transmission, and decrease a transmission speed.

Transmission system

A video signal processing apparatus processes input video signals. A video signal source supplies the input video signals carrying at least a first video signal that is an interlaced signal having 480 effective scanning lines and a second video signal that is an interlaced signal having 1080 effective scanning lines. A video signal processor converts at least the first and the second video signals into a third video signal that is a progressive signal having 1440 effective scanning lines, thus outputting the third video signal. The output third video signal may be converted into a fourth video signal that is an interlaced signal by a progressive-to-interlace converter, thus outputting the fourth video signal.

Video signal processing apparatus and video displaying apparatus

An automatic color control and chroma killer circuit 3 and video processing system is provided that is capable of controlling an amplitude of a color signal and of performing a killer function with a simple construction without using a divider and/or vertical filter. The ACC/ACK device includes ACC and ACK circuitry which may be selectively enabled with operating signals to a selector 27. When the selector 27 enables amplitude detector 25, the amplitude detector 25 detects amplitude of the input color signal and a coefficient controller 26 compares it with a killer level. If the input color signal fails to meet the killer level then the coefficient controller 26 controls a coefficient generated by the coefficient generator 22 to perform a killer operation. The ACC operation and circuitry is thereby ACK controlled until an input color signal meets or exceeds the killer level. When the selector 27 enables the multiplier circuit 11 according to an operating signal input, the input color signal is ACC controlled by the multiplier circuit 11, and amplitude detector 21, a coefficient generator 22, a coefficient memory 23 and a delay circuit 24.

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Kasukabe, Japan

Masafumi Yugami