Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Other

Sanyo Semiconductor Co., Ltd.

Masafumi Uehara

Shuichi Kikuchi

Katsuyoshi Anzai

Eiji Nishibe

Gordon M Grivna

Ali Salih

Masaaki Momen

Thomas Keena

Toshihiro Hachiyanagi

Hiroshi Ishizeki

Daniel R Heuttl

Osamu Ishimaru

A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

Monolithic series switching semiconductor device having low-resistance substrate contact structure and method

A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG.

Semiconductor device having drain/source surrounded by impurity layer and manufacturing method thereof

In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.

Semiconductor device and manufacturing method thereof

A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N-type drain layer is not formed under an N-type drain layer, while a P-type buried layer is formed in a region under the N-type drain layer. A PN junction of high impurity concentration is formed between the N-type drain layer and the P-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Manufacturing method of semiconductor device with protection against electrostatic discharge

Semiconductor device

A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film. Thus the ion-implantation process for the threshold voltage adjustment of a semiconductor device having gate insulation films of different thicknesses can be rationalized with this invention.

Manufacturing method of semiconductor device

Growing community of inventors

Oizumi-machi, Japan

Masafumi Uehara