Matsushita Electric Industrial Co., Ltd.

Masafumi Sato

Kiyokazu Hashimoto

Akihiko Nakamura

Makoto Mitsuda

Masao Okabe

Shozo Fujii

Junji Soga

Tsutomu Miyoshi

Masato Izawa

Katsuyuki Tamai

A playback clock extracting device having: a quantization member for quantizing, at a sampling clock rate having a rate twice a recording rate, a signal played back from a recording medium so as to output sample data, a digital equalizer for subjecting the sample data to digital equalization so as to alternately output playback data and PLL data at an interval of one sampling clock, cycle a ternary decision member for making a ternary decision as to whether the playback data is positive, zero or negative. The playback clock extracting device further having arithmetic unit for calculating a sampling phase error in the quantization member by multiplying a result of the decision of the ternary decision member by a difference between two successive data values of the PLL data outputted immediately prior to and immediately after the playback data for the decision of the ternary decision member, respectively, a sampling clock generating member which controls a phase and an oscillation frequency on the basis of the sampling phase error outputted by the arithmetic unit so as to generate the sampling clock, and a playback clock generating member which divides a frequency of the sampling clock by two so as to generate a playback clock for detecting the playback data.

Playback clock extracting apparatus

An external expansion bus interface circuit is provided for connecting a peripheral to a micro control unit to exchange digital information under an external expansion memory mode of the micro control unit. For this purpose, the eternal expansion bus interface circuit includes a means for storing a writing data. Address decoder and a strobe decoder are connected to the micro control unit to directly receive the writing data, an address strobe, and a write strobe. Then the address decoder and strobe decoder produce a write enable signal for enabling the memory to store the data at address designated thereby.

External expansion bus interface circuit for connecting a micro control

There is provided a data memory apparatus which can efficiently use a general-purpose DRAM as a memory used during the digital data error correcting and modifying processing. The apparatus is comprised of a DRAM, a DRAM access unit and an error correcting circuit. Input digital data is first subjected to the error correcting processing by means of the error correcting circuit, assigned with a result of the error correcting processing and transferred to the DRAM access unit. The DRAM access unit accesses the DRAM in a page mode to store the data in the DRAM.

Data memory apparatus

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Ibaraki, Japan

Masafumi Sato