Mitsubishi Denki Kabushiki Kaisha

Masafumi Kimata

Natsuro Tsubouchi

Tomohiro Ishikawa

Yoshiyuki Nakaki

Naoki Yutani

Masao Yamawaki

Hisatoshi Hata

Kazuhiko Tsutsumi

Satoshi Yamakawa

Masashi Ueno

Masahiko Denda

Sotoju Asai

A method of manufacturing an infrared image sensor in which an etching gas is introduced through etching holes into a semiconductor substrate to form a hollow portion. The etching gas is introduced only through an etching hole in a splicing pillar when etching is started. This method provides an etching configuration which has a largest depth right beneath the splicing pillar and which becomes shallower toward ends of the substrate, and therefore there is no need for forming deep etching stoppers.

Method of manufacturing semiconductor device and method of manufacturing infrared image sensor

A thermal infrared-detector array has semiconductor-junction elements as detectors. It has high sensitivity and low noise and is fabricated in semiconductor-fabrication process. The semiconductor-junction elements are located in a monocrystalline silicon layer overlying a silicon-oxide layer on a monocrystalline silicon substrate. A signal-output circuit reading out signals from the detector elements includes transistors located on the monocrystalline silicon substrate.

Thermal infrared-detector array and method of fabrication thereof

Infrared solid-state imaging elements include an infrared absorbing section formed as to correspond to each pixel aligned in a two-dimensional pattern for absorbing incident infrared radiation and converting the same into heat. A temperature detector section is formed as to correspond to each pixel on a semiconductor substrate and are arranged of a plurality of serially connected silicon pn junction diodes that are biased in a forward direction. A hollow section is formed on each region on which the temperature detector section is formed on the semiconductor substrate. Supporting mechanisms are arranged of materials exhibiting large thermal resistance and which support the temperature detector portion above the hollow section on the semiconductor substrate. A joint column thermally couples the infrared absorbing section and the temperature detector section.

Infrared solid-state imaging sensing device

A two-dimensional infrared focal plane array of temperature detecting units is provided with the temperature detecting units being arranged for every pixel in a two-dimensional arrangement on a semiconductor substrate. Each temperature detecting unit is formed integrally with readout circuitry. Each temperature detecting unit further has a temperature detecting portion which is supported by support legs made of a high thermal resistance material to reduce heat flow to the semiconductor substrate. Each temperature detecting unit also has a temperature detecting element with an infrared ray absorbing portion which is spliced by at least one splicing pillar with the temperature detecting element.

Infrared focal plane array

A focal plane array comprising two-dimensionally arranged photodetectors, charge transfer devices, transfer gates and a pixel row selection circuit, the focal plane array being operated in such a manner that the signal charges are read out from the photodetectors to vertical charge transfer device in one horizontal retrace period and the signal charges stored in the vertical charge transfer device are transferred to outside of a photodetector array region, wherein the pixel row selection circuit comprises a shift register and a switching transistor connected between the shift register and the transfer gates; and by combination of driving the shift resister and driving the switching transistor the horizontal line is selected so that a photodetector from which signal charge is to be read out is selected.

Focal plane array and driving method therefor

A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion below the sensing-element portion, in which a removal resistance region having resistance against substrate removal is provided in the silicon substrate between the semiconductor circuit and the cavity portion.

Sensor element with removal resistance region

A solid state image sensor of charge sweep architecture comprises photodetectors in two-dimension, vertical charge transfer elements and a horizontal charge transfer element. A driver circuit for the vertical charge transfer elements mounted in the solid state image sensor comprises a circuit for setting initial states of shift registers and a circulation loop line connecting an output of the shift register at the last stage to an input of the shift register at a first stage. Thus, a lower consumption power and high efficiency charge transfer are provided in the solid state image sensor.

Solid state image sensor transferring charges with high efficiency and

A solid-state imaging device includes a two-dimensional array of photodetectors, a TG scanner outputting a selection pulse for reading out signal charges stored in the photodetectors, an interlace circuit receiving the selection pulse from said TG scanner and converting the selection pulse to a field storage mode operation pulse or to a frame storage mode operation pulse, and an interlace switching circuit receiving the pulse from said interlace circuit and switching the array of photodetectors between the field storage mode and the frame storage mode. The switching between the frame storage mode and the field storage mode is controlled by an external control signal. Therefore, the solid-state imaging device can select an optimum interlace system according to background conditions and the brightness and size of objects imaged.

Solid-state imaging device

An infrared image sensor includes a plurality of Schottky type infrared detecting elements (8) arranged in array formed on one main surface of a semiconductor substrate (1a) or in a vicinity of the one main surface to allow incident infrared rays from the other main surface of the semiconductor substrate (1a). In this infrared image sensor (1), a high concentration impurity layer (12) is provided between one main surface and the other main surface of the semiconductor substrate (1a), which layer being provided with an infrared ray transparent aperture for the corresponding predetermined unit of the grouped infrared detecting elements (8). According to the infrared image sensor (1), by making the aperture of the high concentration impurity layer (12) into a predetermined configuration at a predetermined position determined by the positional relation between an optical system irradiated by the infrared rays and each detecting element, it is possible to allow only the infrared rays in the desired field to irradiate each infrared detecting element (8) and prevent undesired incident light, thereby improving the efficiency in removing the undesired light and reducing noise.

Infrared image sensor and image pick-up apparatus using the same

An image sensor using a charge sweep device as a vertical transfer device (3) and comprising a plurality of pixels (10) each of which is formed of a single photo-electro transforming element (1) and a single transfer gate (4) for transferring a signal charge from the photo-electro transforming element into the charge sweep device (3), wherein the width of the transfer gate (4) is equal to or larger than that of the photo-electro transforming element in the direction of charge transfer in the charge sweep device (3).

Charge sweep solid-state image sensor

A method of driving a charge detection circuit of floating diffusion amplifier type including, a second conductivity type diffusion region produced on a first conductivity type semiconductor substrate or layer, a voltage barrier gate electrode adjacent the diffusion region, a CCD final gate electrode adjacent the voltage barrier production gate electrode, an MOS transistor for resetting the diffusion region incorporating the diffusion region as a source electrode, a source follower circuit for receiving the voltage of the diffusion region as an input signal. When the signal charges are transferred to the voltage well below the CCD final gate electrode, only the charges exceeding a voltage barrier below the voltage barrier gate electrode are output to the diffusion region.

Method of driving a charge detection circuit

Vertical transfer portions are provided for the respective columns of photodetectors arranged in a matrix. A charge transfer direction of every other vertical transfer portions is opposite to that of the remaining vertical transfer portions. The charges transferred in the opposite directions are outputted in different horizontal transfer portions. The charges transferred by the two horizontal transfer portions are outputted therefrom and brought together in a united form so as to be continuously outputted.

Solid-state image sensor having a plurality of horizontal transfer

A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Process for manufacture of a semiconductor memory device

Diffusion self-aligned MOS transistors are applied to a solid state image sensing device so as to form in a self-alignment manner control regions (80) in which reading of signal charges from photosignal detecting regions (70) formed on a semiconductor (1) to charge transfer regions (30) is controlled.

Solid state image sensing device and a method of manufacturing the same

A charge-coupled device comprises a p type silicon substrate (130), a plurality of n type impurity regions (121) of a high impurity concentration, a plurality of n type impurity regions (140) of a low impurity concentration, a silicon oxide film (150) for defining a channel region (10), a gate oxide film (110), a plurality of gate electrodes (21, 31, 41, 51, 22, 32, 42 and 52) and clock bus lines (70, 80, 90 and 100) for applying a clock signal to the respective gate electrodes. The n type impurity regions (121) and (140) are formed alternately in the channel region (10) along a direction perpendicular to the charge transfer direction, whereby the potential in the channel region (10) changes in the above described perpendicular direction. The change of the potential causes a strong electric field in the channel region (10) in the above described perpendicular direction, which serves to prevent carriers from freezing to an impurity level at a low temperature. Thus, the transfer efficiency of carriers is improved.

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Tokyo, Japan

Masafumi Kimata