Other

Hitachi, Ltd.

Dai Nippon Printing Co., Ltd.

Renesas Technology Corp.

Elpida Memory, Inc.

Hitachi Ulsi Systems Co., Ltd.

Nitto-denko Corporation

Ps4 Luxco S.a.r.l.

Hitachi Vlsi Engineering Corp.

Renesas Electronics Corporation

Hitachi Microcomputer Engineering, Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Tobu Semiconductor

Akita Electronics Systems Co., Ltd.

Renesas Technologies Corporation

Masachika Masuda

Tamaki Wada

Hirotaka Nishizawa

Michiaki Sugiyama

Toshio Sugano

Toshihiko Usami

Akihiko Iwaya

Yasushi Takahashi

Masayasu Kawamura

Hiromichi Suzuki

Chikao Ikenaga

Koji Tomita

Kenji Osawa

Junichiro Osako

Haruji Ishihara

Kazunori Furusawa

Kouichi Kanemoto

Kazuo Yoshizaki

Satoshi Hatakeyama

Kunihiro Tsubosaki

Gen Murakami

Kazuyuki Miyano

Susumu Baba

Atsushi Kurahashi

Asao Nishimura

Satoshi Nakamura

Susumu Hatano

Yutaka Kagaya

Masaki Yazaki

Toshihiro Shiotsuki

Yo Shimazaki

Toshihiro Yasuhara

Takao Ikezawa

Chikako Imura

Satoshi Shibasaki

Tsutomu Wada

Kazuhito Uchiumi

Hiroyuki Saito

Kenji Matsumura

Masaru Fukuchi

Kunihiko Nishi

Sueo Kawai

Kazuhito Hosokawa

Takafumi Nishita

Takuji Okeyui

Kazuhiro Ikemura

Tomoko Higashino

Keisuke Yoshikawa

Hiroshi Ohno

Mikako Kimura

You Shimazaki

Kazuki Sakuma

Hajime Sato

Hideo Miura

Atsushi Nakamura

Makoto Kitano

Akihiro Yaguchi

Mitsuaki Katagiri

Kazunari Suzuki

Takahiro Naito

Junichi Saeki

Isamu Yoshida

Ichio Shimizu

Naoya Kanda

Shigeharu Tsunoda

Akira Suzuki

Tomoaki Kudaishi

Kazunori Oda

Ritsuro Orihashi

Kunio Matsumoto

Wahei Kitamura

Takayuki Okinaga

Michifumi Kawai

Hideo Yamakura

Hiroshi Ohsawa

Ikuo Kawaguchi

Takashi Emata

Ichiro Miyano

Akio Hoshi

Naozumi Hatada

Sumio Okada

Tooru Yoshida

Koich Iro Kagaya

Shuichiro Azuma

Yashuhisa Hagiwara

Masanori Sakimoto

Tadashi Okamoto

Tooru Nagamine

Yasunori Tanaka

Mikako Ujiie

A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.

Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device

A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.

Resin-sealed semiconductor device and associated wiring and support structure

For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.

Method of manufacturing a semiconductor device

A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.

Semiconductor device and manufacturing method therefor

A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.

Semiconductor device and a method of manufacturing the same

Wiring device for semiconductor device, composite wiring device for semiconductor device, and resin-sealed semiconductor device

A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member

A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Plastic package and method of fabricating the same

A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.

A semiconductor composite wiring assembly includes a wiring assembly and a lead frame. A copper wiring layer of the wiring assembly includes first terminals, second terminals, and wiring sections connecting the terminals. The second terminals and the lead frame are electrically connected by connecting members. The lead frame includes a die pad for mounting the wiring assembly, and lead sections located at outer positions. The die pad includes a central area in which a semiconductor chip is mounted via the wiring assembly, and a peripheral area connected to the central area with spaces formed therebetween that serve as resin-seal inflow spaces. The wiring assembly is positioned over the central area and the peripheral area so as to cover the central area completely and the peripheral area partially, and at least the central area and the peripheral area of the die pad are glued to the wiring assembly by resin paste.

Semiconductor wiring assembly, semiconductor composite wiring assembly, and resin-sealed semiconductor device

A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces, each having an average roughness Ra of 0.3 &#x3bc;m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.

Circuit member, manufacturing method of the circuit member, and semiconductor device including the circuit member

Growing community of inventors

Tokorozawa, Japan

Masachika Masuda