Texas Instruments Corporation

Masaaki Yashiro

Clarence W Teng

Shigeki Morinaga

Donald J Coleman, Jr

Gishi Chung

Bing-Whey Shen

Randy McKee

Kiyoshi Shirai

The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

High density dynamic RAM cell

The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.

Method of making trench DRAM cell with stacked capacitor and buried

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Plano, TX, United States of America

Masaaki Yashiro