Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Masaaki Tanimura

Osamu Hashimoto

Yasuyuki Tanaka

Yasuhiro Konishi

Koji Suzuki

Mitsuhiro Hamada

A semiconductor device includes a temperature sensor circuit having a sensor element, internal circuits, sensor terminals connected to the sensor element, and normal terminals connected to the internal circuits. A semiconductor inspection apparatus inspects, by using a probe card having first probes and second probes, the semiconductor device mounted on a stage in a first state in which the first probe is in contact with the sensor terminal and the second probe is not in contact with the semiconductor device and in a second state in which the first probe is in contact with the sensor terminal and the second probe is in contact with the normal terminal. The semiconductor inspection apparatus measures an output value of the sensor element in the first state to calculate temperature characteristics of the sensor element, and grasps a temperature of the sensor element in the second state based on the temperature characteristics.

Method of inspecting semiconductor device, semiconductor device, and probe card

A semiconductor device includes a temperature sensor, a scan control circuit which generates scan chain selection information in accordance with a measurement result of the temperature sensor, a clock control circuit which generates one or more scan chain clock signals based on an external clock signal and the scan chain selection information, a pattern generation circuit which generates a test pattern, and a logic circuit which includes a plurality of scan chains and which receives the scan chain clock signals and the test pattern. The clock control circuit generates the scan chain clock signal in association with each scan chain. During a burn-in test, the logic circuit captures the test pattern into the scan chain associated with the scan chain clock signal.

Semiconductor device and burn-in test method thereof

An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit.

A/D converter and semiconductor device

A semiconductor integrated circuit includes a pin section, internal circuits, an interface section, an expectation value generation circuit, a comparison circuit and a waveform generation circuit. In a first test mode, the expectation value generation circuit generates expectation values of operation signals to be generated by the interface section when first test signals having the same waveform are input via respective pins of the pin section, and the comparison circuit compares operation signals that are actually produced by the interface section with the respective expectation values and produces comparison results. In a second test mode, the waveform generation circuit supplies second test signals to the interface section, and the interface section outputs test output signals having the same waveform to the external system via respective pins of the pin section.

Semiconductor integrated circuit and test system for testing the same

In a testing board ( C), one end of each of a plurality of first wirings ( ) and one end of each of a plurality of second wirings ( ) are connected to a common point ( ). The other end of each of the second wirings ( ) is connected to a terminal ( ) of a semiconductor device ( ) under test. The second wirings ( ) have almost the same length. Signals outputted from drivers of a tester pin ( ) to the first wirings ( ) are composed at the common point ( ), and the composite wave is inputted to the terminal ( ) through each of the second wirings ( ). A relay ( ) is provided at a midpoint of each of the second wirings ( ) and is controlled such that the signals can be inputted to, for example, the terminal ( ) from the driver of the tester pin ( ) through one of third wirings ( ).

Testing apparatus including testing board having wirings connected to common point and method of testing semiconductor device by composing signals

Versatility of an inspection apparatus suitable for use in a burn-in inspection operation is improved so as to enable inspection of various semiconductor integrated circuits. A plurality of relay pins which are electrically connected to wiring patterns laid on a base board are provided. Sockets for receiving a semiconductor integrated circuits are mounted on a base board. An exchange board is provided for electrically connecting socket terminals of the socket to specific relay pins. The exchange board is mounted on the base board via spacers. In accordance with the type of semiconductor integrated circuits, the exchange board and the socket are replaced.

Apparatus and method of inspecting semiconductor integrated circuit

An apparatus to be inspected is mounted on one surface of a socket board. An auxiliary inspecting apparatus for adjusting timing of write signals transmitted from a semiconductor inspecting apparatus is mounted on the other surface of the socket board. Input/output (I/O) pins of the auxiliary inspecting apparatus are connected to corresponding I/O pins of the inspected device via through holes in the socket board on a one-to-one basis. This semiconductor inspecting method is thus capable of easily suppressing the delay difference between a plurality of signals output from the semiconductor inspecting apparatus.

Semiconductor inspecting system for inspecting a semiconductor integrated circuit device, and semiconductor inspecting method using the same

A coincidence detection circuit is furnished to check whether a plurality of output signals read from a plurality of memory cell arrays CELL through CELL coincide with one another. A representative output buffer is provided to have the output signal from the cell array CELL reach a representative pin DQ if the output signals are judged to coincide with one another, and to block the output signal from the cell array CELL while putting the representative pin DQ in a high-impedance state if the output signals are not judged to coincide. Input/output pins DQ through DQ are furnished with ordinary output buffers

Semiconductor integrated circuit and method for testing the same

In a DRAM, a first selector selects one bit of data out of four bits of data read from a memory portion, and provides the data to a data output buffer. Data output buffer is controlled by an output enable signal generated from a determination signal and the like, provides to a data input/output terminal the data from first selector when the four bits of data all match, and causes the data input/output terminal to enter the high impedance state when no match occurs. Since a second selector for selecting either one of read data and determination signal is no longer required, the delay of read data caused by the second selector can be eliminated so that a higher access speed can be achieved.

Semiconductor memory device having a test mode and semiconductor testing method utilizing the same

An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.

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Tokyo, Japan

Masaaki Tanimura