Nec Corporation

Nec Electronics Corporation

Nicca Chemical Co., Ltd.

Elephantech Inc.

Masaaki Sugimoto

Mikio Tanaka

Tohru Tsujide

Takehiko Hamada

Hiroyuki Hamada

Miyako Nakayama

Mitsuo Matsuda

A color hazing or decoloring agent including at least one compound selected from compounds represented by formula (1) and compounds represented by formula (2), and used for color hazing or decoloring of a fabric printed or dyed with a disperse dye:ROOC—X—COOR  (1)YO-(AO)—Y  (2)

Color hazing or decoloring agent and method of producing fabric

In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.

Failure analysis system of semiconductor memory device

Provided are a device, method and storage medium, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, automatically interprets results, and calculates the period of distribution patterns and the mix rate of regular patterned defects. The total defect number of bits is found, and the factor f, is selected. The value of expected value functions, T(f), for the selected f is found, and if it is decided that regularly patterned defects are included, then regular pattern defect mix rate function MR(f) is calculated from number of bits, factor f, and the value of estimated value function T(f). If it is decided that it does not contain regularly patterned defects the regular patterned defect mix rate function MR(f) is assumed to be zero; and it is confirmed whether or not MR(f) has been found for every f.

Memory LSI failure analysis apparatus and analysis method thereof

A method of analyzing a distribution of fault elements is applied to a semiconductor integrated circuit including a plurality of elements which are repeatedly arranged in a pitch of one length unit in a specific direction. The method is accomplished by generating a position of each of fault elements in the semiconductor integrated circuit, and by performing a first determination of whether an appearance expectation function value is larger than a reference value, for each of divisors of the number of length units between fault elements, the number of length units being larger than one length unit. Also, the method is accomplished by performing a second determination of whether a distribution of the fault elements includes a regular distribution, based on the appearance expectation function value and a reference value, and by representing the determining result of the second determination.

Fault distribution analyzing system

An apparatus and a method for inspecting and analyzing a semiconductor integrated circuit can qualitatively and quantitatively distinguish defects caused by design and other defects by analyzing the kind and frequency of divisors between intervals of respective faulty elements. An interval &verbar;&Dgr;x&verbar; in an X-direction, an interval &verbar;&Dgr;y&verbar; in a Y-direction and an interval &verbar;&Dgr;xy&verbar; derived by mulitplying the X-coordinate and the Y-direction between faulty elements with each other in an XY orthogonal coordinate system are calculated. Divisors for respective values of the intervals &verbar;&Dgr;x&verbar;, &verbar;&Dgr;y&verbar; and &verbar;&Dgr;xy&verbar; and number &Sgr;m of each divisor, are calculated. A relationship between a distribution of the faulty elements and a design standard for the kind and number &Sgr;m of the divisors for circuit being tested is evaluated.

Inspection and analyzing apparatus for semiconductor integrated circuit and inspection and analyzing method

An intelligence data base,stores interconnection information and position information on the basis of a substrate about a decoder for an LSI memory cell and memory cells and further stores a program for judging whether the memory cell regarded as defective by a electric testing device,is really defective. A defect data separating computer,refers to the intelligence data base,about whether the memory cell regarded as defective by the electric testing device,is really defective. On this occasion, the intelligence data base,judges whether the memory cell in concern is truly defective and subsequently designates the memory cell's as position on the substrate according to the position information.

Apparatus and method for analyzing circuit test results and recording medium storing analytical program therefor

A failure analyzer has an electric characteristic inspection system for producing pieces of electric test data information for integrated circuit devices fabricated on a semiconductor wafer, a visual inspection system for producing pieces of appearance test data information for the semiconductor wafer and a data analyzing system for producing a failure analysis report from the pieces of electric test data information and the pieces of appearance test data information, and the data analyzing system is implemented by using a client-server network technology so as to increase a data processing capability depending upon the amount of data to be analyzed.

Failure analyzer with distributed data processing network and method

An object of the present invention is to provide a device for and a method of searching a really defective cell by removing influence of poor accuracy of a stage shifting mechanism or a numerical operation error of the device. The method of the present invention is a method of searching a specific cell of memory LSI, said method being employed in performing analysis, processing and observation operation with reference to a part of a physical address which corresponds to a logical address outputted as a result of an electrical test performed on memory LSI of array structure in which a plurality of memory cells are repeatedly arranged. Further, position coordinates are continuously observed with reference to an area including the end point of the array structure of said memory cell, the memory cells and a part between the memory cells; the number of memory cells on memory cell LSI is counted according to changes in brightness or luminosity; and a part in which said counted value and the value shown by said physical address coincide with each other is selected as the part of said logical address.

Specific part searching method and device for memory LSI

An automatic testing apparatus includes an expert rule which is derived from expert knowledge and defines a tree of successively traceable nodes interconnected by decision branches which lead to a plurality of fault modes. Each of the nodes defines a particular test pattern and a corresponding expected value. One of the nodes is specified and a test pattern defined by the specified node is applied to an LSI chip under test and a result signal is derived therefrom. This result signal is compared with the expected value defined by the specified node to produce a comparison result. The tree of the expert rule is traced from the specified node to a subsequent node according to the comparison result and the subsequent node is specified instead of the previously specified node. The process is repeated as the tree is traced from one node to another until one of the fault modes is reached to identify a chip failure.

Growing community of inventors

Tokyo, Japan

Masaaki Sugimoto