Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Intellectual Property Co., Ltd.

Masaaki Nishijima

Osamu Ishikawa

Taketo Kunihisa

Daisuke Ueda

Tsuyoshi Tanaka

Takeshi Fukuda

Shinji Yamamoto

Takahiro Yokoyama

Xinbing Liu

Hiroyuki Sakai

Yorito Ota

Ming Li

Junji Ito

Junji Itoh

Kaoru Muramatsu

Toshio Fujiwara

Chinatsu Adachi

A semiconductor device includes a semiconductor chip, a dielectric substrate, and bonding wires. The dielectric substrate includes wiring patterns formed on a surface and a ground metal layer formed on a back side. The semiconductor chip includes an active element and a drain pad that is connected to an output end of the active element. Wiring pattern is formed at a position closer to the drain pad than wiring pattern, wiring pattern and the ground metal layer constitute a first capacitative element, and wiring pattern and the ground metal layer constitute a second capacitative element. The drain pad is connected to wiring pattern through bonding wire, and connected to wiring pattern through bonding wire. Bonding wire and the first capacitative element constitute a high-pass matching circuit.

Semiconductor device

A semiconductor device includes: a die pad comprised of a metal, and having at least one cutout portion in its peripheral edge portion, and a protruding portion formed by the cutout portion so as to protrude laterally from the peripheral edge portion; an inner lead having at its end a bonding pad that is placed in the cutout portion with an interval between the bonding pad and the die pad; a semiconductor chip held on the die pad so that a center position of the semiconductor chip is located on the protruding portion side with respect to a center position of the die pad; and a wire configured to electrically connect the semiconductor chip to the bonding pad.

A semiconductor device includes: a semiconductor element; a divider connected with an input portion of the semiconductor element; and a combiner connected with an output portion of the semiconductor element. The divider is disposed on a substrate and has a first divider portion including a first transmission line and a second transmission line, a second divider portion including a third transmission line and a fourth transmission line, and a first resistance and a second resistance respectively connected to both the first transmission line and the third transmission line. The first resistance is disposed in the space between the first and third transmission lines, the second resistance is disposed in the space between the first and third transmission lines, and the first resistance is disposed between the second resistance and the semiconductor element.

Semiconductor device having first and second resistance for suppressing loop oscillation

A method for forming a via in a sapphire substrate with a laser machining system that includes an ultrafast pulsed laser source. The sapphire substrate is provided. Pulses of laser light are substantially focused to a beam spot on the first surface of the sapphire substrate such that each focused pulse of laser light ablates a volume of the sapphire substrate having a depth less than the substrate thickness. The beam spot of the focused laser light pulses is scanned over a via portion of the first surface of the sapphire substrate. The sapphire substrate is moved in a direction substantially normal to the first surface to control the volume of the sapphire substrate ablated by each pulse of laser light to be substantially constant. The pulsing and scanning steps are repeated until the via is formed extending from the first surface to the second surface of the sapphire substrate.

Via hole machining for microwave monolithic integrated circuits

A radar apparatus includes a PN code generator for generating a PN code, a variable delay device for delaying the PN code, an oscillator for generating a high-frequency signal, a transmission frequency multiplier for multiplying a frequency of a transmission differential signal obtained by being divided from the high-frequency signal by 3, a reception frequency multiplier for multiplying a frequency of a reception differential signal obtained by being divided from the high-frequency by 3, a transmitter for generating a radar wave by using the differential signal obtained through the multiplication by the transmission frequency multiplier and the PN code generated by the PN code generator, and a receiver for generating an in-phase signal and a quadrature signal from a reflected wave by using the differential signal obtained through the multiplication by the reception frequency multiplier and the PN code delayed by the delay device.

Radar apparatus

A semiconductor integrated circuit device includes a HFET formed on part of a substrate made of sapphire and including a Group III-V nitride semiconductor layer, a dielectric film formed on the substrate to cover the top and side surfaces and upper corners of the Group III-V nitride semiconductor layer, a microstrip line formed with the dielectric film interposed between the substrate and the microstrip line, and a drain lead which is formed on part of the dielectric film and through which the HFET is electrically connected to the microstrip line.

Semiconductor integrated circuit device and vehicle-mounted radar system using the same

An input matching parallel inductorwhich utilizes a spiral inductor, and an input matching parallel capacitorwhich utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion, form an input matching parallel capacitorinside an input matching circuit via-holebeing formed by applying a method of surface via-hole to the front surface of a GaAs substrate. A choke inductorwhich utilizes a spiral inductor, and a bypass capacitorwhich utilizes an MIM capacitor, both being constituting elements of a drain voltage feeding circuit, form a bypass capacitorinside a drain voltage feeding circuit via-holeformed by applying a method of surface via-hole to the front surface of the GaAs substrate. A drain voltage terminalis extended by a drawing wirefrom between the spiral inductor and the drain voltage feeding circuit via-hole

RF passive circuit and RF amplifier with via-holes

A semiconductor device in which an inductance element formed in a resin package has stable characteristics, impedance matching is achieved easily, and the stability of high-frequency characteristics is improved, more particularly a semiconductor chip sealed within mold resin having a conductor lead extending from an inside of the mold resin to an outside. A portion of the conductor lead inside the mold resin forms an inductance element, at least a part of which is narrower than the external portion of the conductor outside the mold resin.

Semiconductor package with leadframe inductors

An input matching parallel inductor which utilizes a spiral inductor, and an input matching parallel capacitor which utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion , form an input matching parallel capacitor inside an input matching circuit via-hole being formed by applying a method of surface via-hole to the front surface of a GaAs substrate . A choke inductor which utilizes a spiral inductor, and a bypass capacitor which utilizes an MIM capacitor, both being constituting elements of a drain voltage feeding circuit , form a bypass capacitor inside a drain voltage feeding circuit via-hole formed by applying a method of surface via-hole to the front surface of the GaAs substrate . A drain voltage terminal is extended by a drawing wire from between the spiral inductor and the drain voltage feeding circuit via-hole

A semiconductor device according to the present invention includes a line structure formed on a semiconductor substrate. The line structure includes: a conductor layer formed on the semiconductor substrate; a dielectric film formed on the conductor layer; and a conductor line formed on the dielectric film. The dielectric film includes: a first dielectric portion, at least part of the first dielectric portion being located between the lower surface of the conductor line and the upper surface of the conductor layer; and second and third dielectric portions laterally arranged to interpose the first dielectric portion therebetween. The dielectric constant of the first dielectric portion is different from at least one of the dielectric constants of the second and third dielectric portions.

A power amplifier including: a first amplifier PA having an input terminal and an output terminal; a passive circuit PC having an input terminal and an output terminal; and a first switch SW having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW being connected to the input terminal of the first amplifier PA and the other of the multi-throw terminals of the first switch SW being connected to the input terminal of the passive circuit PC This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.

Power amplifier and communication unit

A power amplifier including: a first amplifier PA,having an input terminal and an output terminal; a passive circuit PC,having an input terminal and an output terminal; and a first switch SW,having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW,being connected to the input terminal of the first amplifier PA,and the other of the multi-throw terminals of the first switch SW,being connected to the input terminal of the passive circuit PC,. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.

Growing community of inventors

Osaka, Japan

Masaaki Nishijima