Fujitsu Corporation

Masaaki Nagatsuka

Kenichi Kobayashi

Takeshi Horie

Osamu Shiraki

Toshiyuki Shimizu

Koji Hosoe

Hiroyuki Oka

Kensuke Ishida

Atsuyuki Nikami

A processing system includes a first processing device and a switch device. The first processing device includes a first transmitter configured to transmit a plurality of packets, and a controller configured to acquire first time information indicating a first time at which the transmitting of the plurality of packets started. The switch device includes a first receiver configured to receive at least one of the plurality of packets transmitted from the first processing device and receive the first time information from the first processing device, a second transmitter configured to acquire second time information indicating a second time at which a link-up occurred, compare the second time information with the first time information, and perform a notification to a second processing device of occurrence of error in transmitting of the plurality of packets when the second time is later than the first time.

Information processing system, information processing device, data transfer device, and information processing system control method

A communication control device includes a plurality of inputting units to which a packet is inputted a plurality of outputting units to which the packet is outputted a selector that selects an output packet to output from an identical outputting unit among a plurality of conflict packets having the identical outputting unit as a destination, the plurality of conflict packets being selected among a plurality of packets inputted to the plurality of inputting units, based on priority information set in each conflict packet and a processing unit that updates the respective priority information of unselected packets not selected as the output packet by the selector among the plurality of conflict packets based on weighting information in accordance with a packet size.

Communication control device, parallel computer system, and communication control method

A storage device for storing data, while compressing same value of input data, includes an input processing unit, a data storage, a first-in-first-out memory, and an output processing unit. The input processing unit is configured to, upon receiving an input value, determine whether a data value stored in the data storage at an address location corresponding to the input value is valid. If the data value is invalid, the input processing unit stores an initial value at the address location and stores the input value in the first-in-first-out memory. If the data value is valid, the input processing unit performs an arithmetic operation on the data value and stores the operation result in the address location corresponding to the input value. The output processing unit is configured to read and output the input value stored at a head of the first-in-first-out memory, as well as reading and outputting the data value from the address location of the data storage corresponding to the input value, if one or more input values are stored in the first-in-first-out memory and if the data value stored at the address location of the data storage corresponding to the input value is valid, and to update the data value after the output.

Storage device for storing data while compressing same value input data

The DMA data transfer apparatus includes a memory, a communication controller, a DMA controller having a plurality of DMA engines each of which transfers data by DMA to the communication controller from the memory, and a DMA control unit. The DMA control unit determines a division size of transfer data such that the DMA engine can transfer the data, issues a data transfer directive by the DMA to the DMA controller, and controls data transfer by the DMA. The DMA control unit transmits the determination information for determination of the termination of data transfer to the communication controller. The communication controller determines the termination of data transfer based on the determination information transmitted from the DMA control unit.

Apparatus and method for performing DMA data transfer

An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.

Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events

A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted. If a destination of transmission of the barrier synchronization request message is set when completing a predetermined number of receipts of the barrier synchronization request messages and receipts of a barrier synchronization request message from a self-node, the barrier synchronization request message is transmitted to that destination of transmission. If the transmission destination is not set, the barrier synchronization establishment message is transmitted to the set transmission destination of the barrier synchronization establishment message. When receiving the barrier synchronization establishment message, the barrier synchronization establishment message is also transmitted to the set transmission destination of the barrier synchronization establishment message.

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Kawasaki, Japan

Masaaki Nagatsuka