Mitsubishi Denki Kabushiki Kaisha

Genusion, Inc.

Renesas Technology Corp.

Masaaki Mihara

Natsuo Ajika

Takeshi Hamamoto

Yoshikazu Miyawaki

Shoji Shukuri

Toshifumi Kobayashi

Tadato Yamagata

Taku Ogura

Yasuhiko Taito

Yoshiki Kawajiri

Moriyoshi Nakashima

Takeshi Nakayama

Shinichi Kobayashi

Shinji Kawai

Minoru Ohkawa

Yasushi Terada

Tomoshi Futatsuya

Hiroshi Onoda

Hiroshi Takada

Yasuhiro Yamamoto

Katsumi Dosaka

Satoshi Shimizu

Tomohisa Wada

Mitsuya Kinoshita

Hideyuki Ozaki

Hiroaki Nakai

Hidenori Shirahama

A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg&#x3e;Vsub&#x3e;Vs&#x3e;Vd is satisfied, Vg&#x2212;Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub&#x2212;Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Nonvolatile semiconductor memory

A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Nonvolatile semiconductor memory device and usage method thereof

An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

Nonvolatile semiconductor memory using an adjustable threshold voltage transistor in a flip-flop

The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Nonvolatile semiconductor memory device

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg&#x3e;Vsub&#x3e;Vs&#x3e;Vd is satisfied, Vg&#x2212;Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub&#x2212;Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Nonvolatile semiconductor storage device and method for writing therein

In a pin contact test, a voltage across an external pin is measured by setting a voltage to be supplied to the power supply nodes in input protection circuits in their respective chips at a prescribed amount by means of voltage control circuits and by supplying a prescribed constant current to external pin. Based on the measurement results, a pin contact failure in chips can be detected.

Semiconductor integrated circuit allowing proper detection of pin contact failure

By supplying a clock signal from an OSC to four stages of boosting circuit units connected in series, the boosting circuit units are rendered active. A delay element is inserted in the line of the clock signal to prevent all the boosting circuit units from being rendered active at the same time by one clock signal. Since the boosting circuit unit is rendered active one by one by the provision of the delay element, current congregation from the power supply potential at the circuit element connected closest to the input terminal of the boosting circuit unit of the first stage can be prevented. Thus, a boosting circuit of a high boosting efficiency is achieved.

Boosting circuit configured with plurality of boosting circuit units in series

A transistor operating as a current source supplying a memory cell with a current is configured to operate in a saturation range when a node subjected to a decision as to whether a memory cell has a high or low level has a voltage in a range of no more than a threshold voltage.

Non-volatile semiconductor memory device configured to reduce rate of erroneously reading data from memory cell

A nonvolatile semiconductor memory which is provided with a plurality of memory elements each having a control gate and a floating gate such that data is stored by electron injection to the floating gate and electron emission from the floating gate, including an electric current detecting circuit for detecting a drain current supplied to a drain of each of the memory elements and a voltage control circuit for controlling a gate voltage supplied to the control gate of each of the memory elements, in accordance with the drain current detected by the electric current detecting circuit.

Even in the case where the reference voltage of a reference-voltage generating circuit is adjusted by fuses, a number of fuses are required to be disconnected, and the area of fuse circuits tends to increase for fine adjustment. Therefore, by dividing control signals into one part that are predetermined by fixed wiring and another part that is adjustable by fuse circuits, time required for disconnecting fuses is minimized and fine adjustment is made possible.

Semiconductor device

A semiconductor memory device performs a normal boost operation and increases access speed of the operation. The semiconductor memory device includes: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder that selects one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit that outputs an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit. The first booster circuit is connected to the decoder and supplies boosted voltage to a selected word line based on the activated control signal. The second booster circuit is input the deactivated control signal.

Growing community of inventors

Hyogo, Japan

Masaaki Mihara