National Institute of Advanced Industrial Science and Technology

Agency of Industrial Science and Technology Ministry of International

Masaaki Maezawa

Masahiro Aoyagi

Hiroshi Nakagawa

Mutsuo Hidaka

Takashi Nanya

Itaru Kurosawa

Yoshio Kameda

A quantum bit device according to the present invention includes a first quantum bit substratewhich includes a first superconductive wiringdisposed to have a magnetically coupled portion with a first superconductive magnetic flux quantum biton a surface thereof, a second quantum bit substratewhich includes a second superconductive wiringdisposed to have a magnetically coupled portion with a second superconductive magnetic flux quantum biton a surface thereof, and a base substratewhich includes a third superconductive wiringconfigured by two superconductive wirings extending parallel to each other on a surface thereof. The first and second quantum bit substrates are placed on the base substrate, two end portions of the first superconductive wiring and two end portions on one side of the third superconductive wiring are joined via superconductive solders, two end portions of the second superconductive wiring and two end portions on the other side of the third superconductive wiring are joined via superconductive solders, and three of the first to third superconductive wirings form one continuous superconductive loop.

Quantum bit device

An elementary cell uses single-flux-quanta as two-valued logic propagation signals and is effective for Constructing asynchronous superconducting logic circuits. The elementary cell comprises one OR circuit section and one AND circuit section. Input pulses applied to two input terminals of the elementary cell are split at signal splitting sections in the elementary cell and applied to both inputs of the OR circuit section and both inputs of the AND circuit section. The output of the OR circuit section is defined as the OR output of the elementary cell. A first arrival pulse memory section is provided in the AND circuit section and when one of two input pulses input to the two input terminals of the AND circuit section arrives before the other, this fact is recorded in the first arrival pulse memory section as logical '1'. When the other input pulse arrives while logical '1' is recorded in the first arrival pulse memory section, the AND circuit section produces an AND output which is defined as the AND output of the elementary cell. When a reset signal pulse is applied to a reset terminal, the first arrival pulse memory section is reset.

Elementary cell for constructing asynchronous superconducting logic

Growing community of inventors

Tsukuba, Japan

Masaaki Maezawa