Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

The University of Tokyo

Fuijtsu Limited

Masaaki Kawai

Kazuyuki Tajima

Haruo Yamashita

Hisako Watanabe

Hidetoshi Naito

Tadashi Ikeuchi

Hiroshi Tomonaga

Naoki Matsuoka

Hiroyuki Rokugawa

Yuji Takizawa

Norio Murakami

Tadao Inoue

Toru Matsuyama

Norio Ueno

Makoto Miki

Toshiyuki Takauji

Tomoyuki Ohtsuka

Satomi Ikeda

Takeshi Hoshida

Tsuyoshi Yamamoto

Hiroyuki Fujita

Satoshi Kuroyanagi

Goji Nakagawa

Daisuke Yamazaki

Ryuichi Takechi

Tomoyuki Kato

Shinji Yamashita

Masafumi Katoh

Yutaka Ezaki

Hidenao Nakajima

Hideo Tatsuno

Masayoshi Sekido

Akira Hakata

Yoshimi Watanabe

Miwako Watanabe

Yuji Takigawa

A wavelength converter includes an excitation light source outputting excitation light, a beam splitter receiving an input of the excitation light and an input of the optical signal and to divide both the inputted excitation light and the inputted optical signal into a first polarization component and a second polarization component, a non-linear optical fiber as a non-polarization-maintaining fiber, an accommodation section securing and accommodating the non-linear optical fiber, a first collimator lens disposed between the beam splitter and a first end of the non-linear optical fiber, and a second collimator lens disposed between the beam splitter and a second end of the non-linear optical fiber, wherein the optical signal is inputted to the beam splitter from a direction different from the input of the excitation light.

Wavelength converter and transmission apparatus

An optical module includes a mirror which reflects input light and which outputs output light; and a mirror control section which is opposite to the mirror and which controls, at the time of the input light being reflected from a reflecting surface of the mirror, the reflecting surface by distorting the reflecting surface according to voltage applied to the mirror so as to output the output light an optical coupling characteristic of which changes. By using this optical module, the optical coupling characteristic of the output light changes.

Optical module, optical control method by optical module, optical switch, and optical switching method

Using a switching signal from a coarse/fine switching and operation mode switching circuit, the width of change of a counter control value during power up is increased, and the width of change is reduced once a steady state is reached. In the steady state, the frequency of updating is limited by a control signal from an update permit control circuit. In the steady state, the frequency band of a current source in an LD driving circuit is reduced in width.

Light output control circuit

In a data decision circuit: a clock generation unit generates a clock signal based on a phase difference signal so that the clock signal has an optimum phase with respect to a phase of an input data signal; a data determination unit determines data values carried by the input data signal, by using the clock signal; a phase-difference detection unit detects a rising-side phase difference and a falling-side phase difference, where the rising-side phase difference is a phase difference between a rising of the input data signal and a next transition in the clock signal, and the falling-side phase difference is a phase difference between the transition and a next falling of the input data signal; and a phase-difference-signal generation unit generates the phase difference signal so as to represent a difference between the rising-side phase difference and the falling-side phase difference.

Data decision circuit using clock signal which has phase optimized with respect to phase of input data signal

Light output control device

A plurality of switching modules arrayed in a plurality of columns and in at least one row switch over paths in accordance with path data contained in cells to transfer inputted data to a target line on the cell-unit. One or more path switching units are provided between two adjacent columns of switching modules among plural columns of switching modules and switch paths between the respective switching modules, disposed in a side-by-side relationship in a row direction, of one column of switching modules of the two adjacent columns of switching modules and the respective switching modules, disposed in the side-by-side relationship in the row direction, of the other column of the two adjacent columns of switching modules.

ATM switch and method for switching path by ATM switch

A switching equipment accommodates lines and includes a line interface for processing data from the line on the unit of cell. The line interface has a basic processing unit and an additional processing unit. The basic processing unit performs a basic process on the cell. The additional processing unit separated from the basic processing unit but disconnectably connected to the basic processing unit executes an additional process on the cell. The additional processing unit includes a plurality of processing blocks for effecting a plurality of additional processes on the cells. Each processing block is individually disconnectably connected to the basic processing unit. The basic processing unit includes a selecting portion for selecting, when one or more processing blocks within the additional processing unit are connected, the connected processing blocks and performing the additional process on the cell.

Apparatus for high-speed packet switching in a broadband ISDN

Switching equipment in provided for performing a switching process of a fixed length cell consisting of data and a cell header. A line interface provided in the switching equipment accommodates a plurality of lines and, at the same time, processes the data from each line on a cell unit. The line interface includes individual units and a common unit. The individual units are individually connected to the plurality of lines accommodated therein and individually process the cells. The common unit is connected to the individual units and, at the same time, effects batch-processing of the cells processed by the individual units.

Switching equipment for performing a switching operation for a

A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from the first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit, and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.

Transmission circuit for transmitting fixed-length data

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit. The interface unit has a reception port for receiving an ATM cell or inserting a monitor cell, and a transmission port for transferring the ATM cell or extracting the monitor cell; The multiplexer is operatively connected to corresponding interface unit for multiplexing the monitor cell; The VPI conversion tables is operatively connected to corresponding multiplexer for converting the VPI to change a transmission route of the monitor cell; The switch unit is operatively connected to the VPI conversion tables for switching the transmission route of the monitor cell based on the VPI; The demultiplexer is operatively connected to the switch unit for demultiplexing the monitor cell and transferring the monitor cell to the transmission port; The loop-back unit is operatively connected to corresponding interface unit for changing the transmission route so as to transfer the monitor cell to the same interface unit which the monitor cell is inserted, and as a result, the apparatus can be monitored by comparing the inserted monitor cell with the extracted monitor cell in the same interface unit.

Cross-connection apparatus for B-ISDN

A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

System for monitoring ATM cross-connecting apparatus by inside-apparatus

A circuit for generating a discrimination voltage level V.sub.ref which is used as a reference voltage to discriminate between two adjacent logic levels or an input signal which can have a plurality of different voltage levels generally corresponding to a plurality of respective, different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity (i.e., the voltage range from the level V.sub.ref -.DELTA.V to the level V.sub.ref +.DELTA.V) of the discrimination voltage level (i.e., the 'upper half' thereof being the voltage range from V.sub.ref to V.sub.ref +.DELTA.V, '.DELTA.V' being a predetermined off-set value) and the frequency at which the levels of the input signals lie in the lower half of the vicinity (i.e., as above defined) of the discrimination level (i.e., the 'low half' thereof being the voltage range from V.sub.ref -.DELTA.V to V.sub.ref) are compared, and the discrimination level is controlled so that the above two frequencies are the same.

Circuit for generating discrimination voltage level

A phase shift circuit used in a regenerating repeater, includes a separating unit for separating an input signal into two separate signals having a phase difference of a phase angle of 90.degree. therebetween, one separated signal having a '0' phase and the other separated signal having a '.pi./2' phase. A distributing unit distributes the '0' phase separated signal and '.pi./2' phase separated signal as three distributed signals having phase difference of phase angles of 90.degree. and 180.degree. therebetween, one distributed signal having a '0' phase and the others being a '.pi./2' phase distributed signal and a '.pi.' phase distributed signal. A weighting/compounding unit analyzes the '0' phase distributed signal, '.pi./2' phase distributed signal, and '.pi.' phase distributed signal regarding a plurality of phase signals each having a phase shift extent, compounds each of the phase signals after being weighted by each amplitude, the weighting being performed by a weight control signal applied from an external stage, and generates an output signal adding a phase shift proportional to the weight to the input signal.

Phase shift circuit

Growing community of inventors

Kawasaki, Japan

Masaaki Kawai