Seiko Instruments Inc

Kabushiki Kaisha Daini Seikosha

Agency of Industrial Science and Technology

Interchip Corporation

Seiko Instruments & Electronics Ltd.

Other

Agency Industrial Science

Kogyo Gizyutsuin

Interchip Co., Ltd.

Agency of Industrial Science and Technology and Seiko Instruments Inc.

Masaaki Kamiya

Yoshikazu Kojima

Hiroaki Takasu

Yutaka Hayashi

Kojiro Tanaka

Masayuki Namiki

Yutaka Saito

Kunihiro Takahashi

Tsuneo Yamazaki

Hiroshi Suzuki

Jun Osanai

Kazutoshi Ishii

Masaaki Taguchi

Yasuhiro Moya

Satoru Yabe

Ryoji Takada

Ryuichi Takano

Ryuji Ariyoshi

Atsushi Sakurai

Kenji Aoki

Yutaka Saitoh

Tadao Iwaki

Kunio Nakajima

Katsuyuki Takahashi

Naoto Saito

Mizuaki Suzuki

Hitomi Watanabe

Hitoshi Niwa

Nobuyoshi Matsuyama

Takao Akiba

Yukihiro Imura

Koju Nonaka

Masanori Gouda

Yomoyuki Yoshino

To provide an oven controlled crystal oscillator which can keep constant the temperature of a quartz resonator housed within a thermostatic oven, thereby ensuring stable operation of the quartz resonator. An oven controlled crystal oscillator has a control system for exercising control so that the temperature of a quartz resonator becomes a target temperature Ttarg of a predetermined fixed value. The quartz resonator is housed within a thermostatic oven which is configured to compare a set temperature Tr and a measured temperature Tic based on an outside air temperature measured by a temperature sensor and which is controlled so that a difference between both temperatures is narrowed. The quartz resonator has characteristics influenced by an environmental temperature. The control system adds a predetermined feedback amount &#x3b4;T to the target temperature Ttarg of the fixed value to generate a new set temperature Tr for comparison with the measured temperature Tic so that when the measured temperature Tic lowers, the set temperature Tr becomes high, or when the measured temperature Tic rises, the set temperature Tr becomes low.

Thermostatic oven type electronic instrument

Each of varicapsA toC configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicapsA toC has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicapsA toC is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

Integrated MOS varicap, and voltage controlled oscillator and filter having same

A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.

Nonvolatile memory cell and data latch incorporating nonvolatile memory cell

An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.

AC amplifier and piezoelectric vibrator oscillator

A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.

Inverting amplifier and crystal oscillator having same

A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Semiconductor device and method of fabricating the same

A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.

MOS-type capacitor and integrated circuit VCO using same

Small geometry high voltage semiconductor device

To provide a semiconductor substrate and a light-valve semiconductor substrate capable of preventing the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing and forming a MOS integrated circuit with a high reliability even for a long-time operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer,formed above an insulating substrate,through an adhesive layer,and an insulating layer,formed on the single-crystal silicon thin-film device forming layer, wherein a heat conductive layers,and,made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.

Semiconductor device

In a method of manufacturing a semiconductor chip, a wire is traveled in one way to cut a wafer into a plurality of chips while a wire train where wires are arranged by pitches of scribe lines is brought into contact with the scribe lines of the wafer linearly, and an abrasive solution is supplied to a contact portion thereof.

Method of manufacturing a semiconductor chip

A light valve has a composite substrate comprised of an electrically insulating substrate and a semiconductor single crystal thin film formed over the electrically insulating substrate. A pixel array comprising semiconductor switch elements is formed in the semiconductor single crystal thin film. A peripheral circuit having circuit elements is formed in the semiconductor single crystal thin film so that a small-sized, high speed light valve is obtained. X- driver and Y-driver circuits are formed in the semiconductor single crystal thin film and controlled by a control circuit, such as a video signal processing circuit, which receives and processes video signals inputted directly from an external source. The peripheral circuit can be a DRAM sense amplifier for sensing charges stored in each pixel of the pixel array to detect defects in the pixel array. The peripheral circuit can be a photosensor circuit for detecting an intensity of incident light to monitor the performance of a light source of the light valve. The peripheral circuit can be a temperature sensor for detecting the temperature of a liquid crystal layer of the light valve, and may be comprised of Darlington connected NPN transistors formed in the semiconductor single crystal thin film. The peripheral circuit can also be a solar cell for converting incident light into electrical energy to supply power to at least one of the pixel array, X-driver and Y-driver circuits and the peripheral circuit.

Light valve device

A method of fabricating a light valve device comprises forming a substrate having stacked layers including a light-shielding thin film layer, an insulating film, and a single crystalline semiconductor thin film stacked in this order on a transparent support substrate. A light-shielding layer pattern is formed by selectively etching the stacked layers. Thereafter, a switching element is formed comprised of a transistor having a channel region formed in the single crystalline semiconductor thin film and a main gate electrode covering the channel region. The channel region is provided over the light-shielding pattern layer to prevent light incident from the transparent support substrate from illuminating the channel region to suppress a photo-induced leakage current in the channel region. A transparent electrode is formed and is electrically connected to the switching element. An opposing substrate is then provided over the substrate at the side of the single crystalline semiconductor thin film, and an electro-optical material layer is interposed between the substrate and the opposing substrate.

Method of fabricating semiconductor device having stacked-layered

A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode. In a further embodiment, the peripheral transistor has a drain region and a gate insulating film having a portion of the insulating film that is thinner than the rest of the gate insulating film. In another embodiment, a gate contact is electrically connected between a gate electrode and a metal gate line of the peripheral transistor to reduce a resistance therebetween. In another embodiment, the peripheral transistor has a transistor breakdown voltage that is smaller than a gate breakdown voltage to efficiently release electrostatic stress current.

Semiconductor integrated circuit device with electrostatic damage

A method of fabricating a semiconductor device comprises the steps of sequentially forming a first gate electrode and an insulating film over a transparent support substrate, forming a through-hole in the insulating film, forming a semiconductor single crystal silicon thin film over the transparent support substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region of the transistor element.

Method of fabricating semiconductor device having stacked layer substrate

Growing community of inventors

Tokyo, Japan

Masaaki Kamiya