Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Mitshubishi Electronic Corporation

Masaaki Ikegami

Naoto Kaguchi

Eisuke Suekawa

Yasuki Yoshihisa

Tetsuo Higuchi

Junichi Arima

Hiroshi Mochizuki

Reiji Tamaki

Eisuke Tanaka

Kenji Saito

A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate.

Semiconductor device

The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a nsource layer to sandwich a field insulating film, a second gate electrode being the same layer as a gate polysilicon and formed at least on the field insulating film, a third gate electrode formed on one of portions of the second source layer to be electrically connected to the second gate electrode, and a second source electrode formed on the other portion of the second source layer.

Wide band gap semiconductor device

A jig for use in a semiconductor test of the present invention includes; a base on which a probe pin and an insulating material are provided such that the probe pin is surrounded by the insulating material in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are provided. The stage is capable of receiving a test object placed on a surface facing the base. When the test object is placed on the stage and the base and the stage move in a direction in which they get closer to each other, the probe pin comes into contact with an electrode formed on the test object, and the insulating material comes into contact with both the test object and the stage.

Jig for use in semiconductor test and method of measuring breakdown voltage by using the jig

A jig for use in a semiconductor test includes: a base on which a probe pin and an insulating material are placed, the insulating material surrounding the probe pin in plan view; and a stage arranged to face a surface of the base on which the probe pin and the insulating material are placed. The stage is capable of holding a test object on a surface of the stage facing the base. When the base and the stage move in a direction in which they go closer to each other while the test object is placed on the stage, the probe pin comes into contact with an electrode formed on the test object and the insulating material comes into contact with the test object.

Jig for semiconductor test

A semiconductor device having stable device characteristics, in which variation in contact resistance between silicon and poly-silicon or between poly-silicon and poly-silicon is reduced. In a cleaning process before forming an upper layer poly-silicon film, a treatment is conducted to form a thin uniform oxide film on the surface of silicon. After forming the upper layer poly-silicon filma removed portion is uniformly formed on the thin uniform oxide film by applying a short time, high temperature annealing treatment.

Method of manufacturing a semiconductor device

A semiconductor device in which stable and low resistance ohmic contact can be obtained in a base contact region without decreasing the emitter-base reverse breakdown voltage and the current amplification factor is disclosed. In this semiconductor device, p.sup.++ -type base contact layer 8 having an impurity concentration higher than that of p.sup.+ -type base layer 5 is formed in a region spaced apart by a predetermined distance from n.sup.+ -type emitter layer 7 on the main surface of p.sup.+ -type base layer 5. Thus, p.sup.++ -type base contact layer 8 having a high concentration does not contact n.sup.+ -type emitter layer 7, and also the current amplification factor and the emitter-base breakdown voltage are not decreased. Since p.sup.++ -type base contact layer 8 is formed so as to have a diffusion depth shallower than that of n.sup.+ -type emitter layer 7, the lateral spread of p.sup.++ -type base contact layer 8 can be reduced. Therefore, the side of p.sup.++ -type base contact layer 8 having a high concentration can be effectively prevented from contacting the side of n.sup.+ -type emitter layer 7 even when the elements are made smaller.

Semiconductor device including a bipolar transistor

A method of manufacturing a semiconductor device by forming first and second resistor layers of polycrystalline silicon including impurities on a first insulation film with a predetermined distance therebetween. The resistor layer have a resistance ratio set to a predetermined value. A second insulation film is formed on the first and second resistor layers and has an opening in a predetermined region. A metal layer electrically connected to the first and second resistor layers is formed in the opening and extends onto the second insulation film. The metal layer is patterned to form a first metal interconnection layer electrically connected to the first resistor layer and a second metal interconnection layer electrically connected to the second resistor layer. The first metal interconnection layer partially covers the first resistor layer. The second metal interconnection layer partially covers the second resistor layer. A plasma nitride film is formed on the first metal interconnection layer, second metal interconnection layer, first metal layer and second metal layer. The first and said second metal layers are patterned so that the overlapping area ratio between the first resistor layer and the first metal interconnection layer is substantially equal to the overlapping area ratio between the second resistor layer and the second metal layer.

Method of manufacturing a semiconductor device having polysilicon

The bipolar semiconductor device fabricated according to the present invention have high CB junction breakdown voltage (BV.sub.CBO), small capacitance between collector and base and high response speed. A n.sup.+ type well diffused layer 105 to be a base for vertical type transistor is formed to reach to a p.sup.+ type buried region 104. Further, a p.sup.+ type diffused layer 106 is formed to reach to the p.sup.+ type buried region 104 and to surround the n.sup.+ type well diffused layer 105 at intervals of the distance (d). The product NA(104).times.ND(105) is adjusted to become larger then the product NA(106).times.ND(102) wherein NA(104) is an impurity concentration of said buried layer (104) of said first conductive type to be a collector; NA(106) is an impurity concentration of said diffusion region (106) to be a collector electrode; ND(102) is an impurity concentration of said epitaxial layer (102) of said second conductive type; ND(105) is an impurity concentration of said well region (105) of said second conductive type to be a base for transistor.

Bipolar semiconductor device and fabricating method thereof

n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned directly under field oxide film. A base region and a collector region are respectively formed in the surface of n type epitaxial layer positioned between field oxide films. As a result, a semiconductor device having an IIL circuit is obtained which can suppress the parasitic bipolar operation between base regions, reduce the junction capacitance between the base region and the emitter region and which can be reduced in size.

Method of manufacturing a semiconductor IIL device with dielectric and

A semiconductor device is disclosed that can effectively prevent a change in the resistance ratio of polysilicon resistor films when a plasma nitride film is formed above a plurality of polysilicon resistor films. The semiconductor device has metal interconnection layers 5a and 5b formed above polysilicon resistor films 3a and 3b, respectively. The ratio of the overlapping area of the polysilicon resistor film 3a and the metal interconnection layer 5a is set to be substantially equal to that of the polysilicon resistor film 3b and the metal interconnection layer 5b.

Semiconductor device having polysilicon resistors with a specific

Semiconductor IIL device with dielectric and diffusion isolation

To manufacture a semiconductor device a first insulating oxide film and a second thicker insulating oxide film, which continues to the first insulating oxide film, are formed on a semiconductor substrate. The first and second insulating oxide films are covered by a polysilicon film selectively formed on a patterned nitride layer or formed over the semiconductor substrate. In the second case, a silicon nitride film is formed in the lowermost layer portion of the polysilicon film by implanting nitrogen ions and then applying a heat treatment. The polysilicon and silicon nitride films are patterned for forming first and second polysilicon resistance films on the first and second insulating oxide films, respectively. A first electrode is connected to the first polysilicon resistance film and a second electrode is connected to the second polysilicon resistance film. An insulating protection film formed over the semiconductor substrate covers the first and second polysilicon resistance films and the first and second electrodes.

Method of manufacturing a semiconductor device with hydrogen ion

A thin first insulating oxide film is formed on a semiconductor substrate. A thick second insulating oxide film is formed on a semiconductor substrate. A first polysilicon resistance film is formed on the first insulating oxide film. A second polysilicon resistance film is formed on the second insulating oxide film. An insulating protection film, which contains a large amount of hydrogen ion and covers the first polysilicon resistance film, second polysilicon resistance film, first electrode and second electrode, is formed on the semiconductor substrate. A hydrogen ion intercepting film, which prevents passage of hydrogen ion, is interposed between the first insulating oxide film and the first polysilicon resistance film and between the second insulating oxide film and second polysilicon resistance film.

Semiconductor device with hydrogen ion intercepting layer

An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.

Growing community of inventors

Tokyo, Japan

Masaaki Ikegami