Nuvoton Technology Corporation Japan

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Masaaki Hirako

Ryosuke Okawa

Takeshi Imamura

Kazuma Yoshida

Toshikazu Imai

Eiji Yasuda

Shigetoshi Sota

Mitsuaki Sakamoto

Yasuyuki Masumoto

Tomonari Oota

Ryou Kato

Takashi Ohashi

Masao Hamasaki

Tomonari Ota

Dohwan Ahn

A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer in contact with and connected to an entire back face of the semiconductor layer; and a support bonded to the back face side of the metal layer via a conductive adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a semiconductor chip resulting from excluding the support and the conductive adhesive from the semiconductor device is in a curved shape projecting in a direction away from the support.

Semiconductor device

A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors. The thickness of the backside electrode ranges from 25 to 35 &#x3bc;m, and the ratio of the thickness of the backside electrode to the thickness of a semiconductor layer including the semiconductor substrate and the low-concentration impurity layer is 0.32 or more.

Semiconductor device, semiconductor module, and packaged semiconductor device

A semiconductor device includes: a semiconductor (10 &#x3bc;m&#x2264;t&#x2264;30 &#x3bc;m); a metal layer (30 &#x3bc;m&#x2264;t&#x2264;60 &#x3bc;m) comprising Ag; a metal layer (10 &#x3bc;m&#x2264;t&#x2264;35 &#x3bc;m) comprising Ni; and transistors. The transistors include a source electrode and a gate electrode on the semiconductor layer. The metal layer functions as a common drain region for the transistors. The ratio of the lengths of the longer side and the shorter side of the semiconductor layer is at most 1.73. The ratio of the surface area and the perimeter length of each electrode included in the source electrode is at most 0.127. The cumulative surface area of the source electrode and the gate electrode is at most 2.61 mm. The length of the shorter side of the source electrode is at most 0.3 mm, and 702&#x3c;2.33&#xd7;t+10.5&#xd7;t+8.90&#xd7;t&#x3c;943 is satisfied.

A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

Semiconductor device including first and second metal oxide semiconductor transistors

Growing community of inventors

Shiga, Japan

Masaaki Hirako