Hitachi, Ltd.

Renesas Technology Corp.

Masaaki Fujimori

Tomihiro Hashizume

Masahiko Ando

Takeo Shiba

Yuji Suwa

Masahiro Kawasaki

Noriyuki Sakuma

Yoshio Homma

Seiichi Kondo

Tadashi Arai

Tomoharu Nakamura

Shuji Imazeki

Tohru Kohno

Ken Yamaguchi

Toru Kouno

Yuuichi Nagayama

Koki Morikawa

A power generating system comprising: a plurality of power generating units coupled in parallel; a power collecting device for collecting electric power output from the plurality of power generating units; and wirings for coupling the plurality of power generating units and the power collecting device. A ratio of a conductor diameter to a predetermined length of each of the wirings is defined as a reference ratio. A value obtained by multiplying the reference ratio, a number of the wirings, and a loss generated by a specific wiring together is subtracted from a value obtained by multiplying a predetermined number of wirings for adjustment by a ratio of a conductor diameter to a length of the specific wiring. A total of the ratios of the conductor diameters to the lengths of the predetermined number of the wirings for adjustment is determined as a value less than the subtracted value.

Power generating system and method of designing power generating system

A method for calculating a solar radiation amount is provided, which enables the prediction of a solar radiation amount with consideration also given to the small movement of a cloud that affects a power generation amount generated by a PV array and thereby improves the accuracy of prediction of the power generation amount generated by the PV array. From a measured output value of a solar panel, solar radiation and a temperature parameter are extracted. An output of a PV is calculated from the extracted solar radiation and temperature parameter. The calculated value is correlated with the measured value. A temperature correction coefficient is obtained so that a correlation coefficient is highest, and a solar radiation amount is calculated using the obtained correlation coefficient.

Method for calculating solar radiation amount and method for determining power to be supplied

A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.

Electronic device

An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.

Organic thin film transistor array and method of manufacturing the same

An organic transistor is formed with a low material cost and low manufacturing cost while still providing high performance and a low contact resistance with an organic semiconductor of the transistor. The organic transistor has electrodes whose bodies are formed mainly of an inexpensive first metal and whose surfaces are formed of a second metal that is expensive but provides high performance properties. To obtain stability of this structure with a low cost, a property of the second metal is used in which the second metal is easily segregated on the surface of the first metal in an alloy of the first metal and the second metal.

Wiring and organic transistor, and manufacturing method thereof

In an image display device comprising a display part configured with a plurality of pixels and a peripheral integrated circuit which controls the display part, the display device is provided on a support substrate which has high durability for the impact and the bending, the pixel circuit is configured with an organic semiconductor TFT, the peripheral integrated circuit is configured with a low-temperature poly Si-TFT, this peripheral integrated circuit is provided on a support substrate of the display device being removed the support substrate when being manufactured, and the pixel circuit and the peripheral integrated circuit are connected with the same wire layer.

Thin film transistor device, image display device and manufacturing method thereof

To provide a method of easily producing TFT in which the orientation of channel molecules or wires is enhanced, compared with conventional type organic TFT at a low price, a lyophilic TFT pattern encircled by a lyophobic area is formed on a substrate, spontaneous movement is made in a droplet containing organic molecules or nanowires dropped in a channel region by characterizing the form of the pattern, and the organic molecules or the nanowires are oriented in the channel region by the movement.

Field effect transistor and its manufacturing method

A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a region to be a channel between the source electrode and the drain electrode is provided, a boundary between the region and either one of the source electrode and the drain electrode is linear, a boundary between the region and either one of the drain electrode and the source electrode is non-linear, the boundary has a continuous or discontinuous shape, and the boundary part has a plurality of recess parts, the surface of the region has hydrophilicity and a peripheral region of the region prepares a member having water-repellency, and a solution including semiconductor organic molecules is supplied to the region, and the solution is dried.

Field effect transistor and manufacturing method thereof

A TFT having a large mobility of carriers that are conducted through a channel as compared with a conventional organic TFT, and a method of manufacturing the TFT inexpensively and easily are provided. The channel is formed of a semiconductor organic molecular crystal thin film which is highly oriented, and a TFT that is large in the mobility of the carriers that are conducted through the channel, and a lyophilic TFT pattern that is surrounded by a lyophobic region on a substrate are formed, and the configuration of the pattern is featured, whereby a solution of the semiconductor organic molecules which is supplied to an appropriate region of a substrate surface including the channel is spontaneously dried in an anisotropic fashion, and highly oriented crystal is grown in the drying process.

Field effect transistor having a structure in which an organic semiconductor that forms a channel is made of a single crystal or a polycrystal of organic molecules

Described is a polishing technique adapted for multilevel metallization of an electronic circuit device, which comprises polishing a metal film with a polishing liquid containing an oxidizing substance, a phosphoric acid and a protection-layer forming agent. The present invention makes it possible to polishing a metal film at a high removal rate while suppressing occurrence of scratches, delamination, dishing or erosion.

Polishing method, metallization fabrication method, method for manufacturing semiconductor device and semiconductor device

A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.

Growing community of inventors

Hatoyama, Japan

Masaaki Fujimori