Nec Corporation

Nippon Electric Co., Ltd.

Nippon Telegraph and Telephone Public Corporation

Masaaki Akahori

Yoshio Ichikawa

Daisuke Ishii

Kazuyuki Tsunoda

Koichi Nagata

Takashi Ohyagi

Kazumori Yamada

Hiroshi Watanabe

Yohichiro Minami

Shozo Nishimura

A data display radio pager for receiving a digital paging signal including an address codeword made up of an address bit group and function bits following the address bit group, and a message codeword following the address codeword. A PROM (Programmable Read Only Memory) conventionally incorporated in this type of pager is replaced with an EEPROM (Electrically Erasable Programmable ROM) or similar rewritable memory. The EEPROM allows address codewords designating the pager and alert mode designation codes associated with function bits to be rewritten, as desired.

Data display radio pager

A testable pager including a receiver for demodulating a sequence of signals, and a manually operated switch. A controller receives the outputs of the receiver and the switch. The controller thereby switches on a power supply for the receiver for a set period after the start of the signal sequence. When the sequence includes a test code, the power supply stays on and a first test is performed. Actuations of the switch cause further tests to be made.

Paging receiver having a plurality of test modes

In a pager receiver (12) of a paging system, a reception controller (21) is kept operable when a switch (22) is closed. A first transistor (31) energizes a receiver part (16, 17) at the beginning of a call code part of a received calling signal. If a calling code for that receiver is detected at a certain call time slot of the call code part, the first transistor keeps the energization until the end of that call code part and again energizes the receiver part during a message time slot corresponding to that call time slot in a message code part which next follows that call code part in the received calling signal. A second transistor (32) energizes a display part (26-28) a little before that message time slot. If a message code is detected at that message time slot, the second transistor keeps the energization to generate an alert tone and a visual display. As soon as a blank message pattern is detected at that message time slot, the second transistor suspends the energization. It is preferred that a calling code for any one of pager receivers of the system be placed nearer to the call code part beginning and that a blank call pattern be placed in each call time slot where no calling code is present. As soon as the blank call pattern is detected, the first transistor suspends the energization without waiting the call code part end.

Pager receiver comprising a message detector energized only at pertinent

In a radio communication apparatus comprising a P-ROM (32), a loudspeaker (34), and/or a display unit (36) and carrying out a receiving operation of selectively receiving a call signal specific to the apparatus by the use of an identification number read out of the P-ROM, a predetermined signal to be produced after the call signal is defined to inhibit or disable the receiving operation carried out after reception of the predetermined signal. The loudspeaker may be driven under control of a reception controller (31) to continuously produce an audible signal when the predetermined signal is received. The display unit may also be driven to provide visual displays representative of particular messages conveyed by the predetermined signal. The particular messages may be 'lost' and 'theft' codes and a telephone number.

Radio communication apparatus disabled on reception of a predetermined

A paging receiver includes a noise detector for detecting an external noise component applied to a housing of the paging receiver, and a reset circuit having a timer which is started in response to an output from the noise detector and which generates a reset pulse to reset other components of the paging receiver in the initial standby state.

Paging receiver which is resettable with external-noise detector

A selective call receiver with display is disclosed. The receiver includes a decoder comprised of a reception controller in the form of a dedicated LSI circuit and a display controller in the form of a single chip CPU which, in combination, overcomes inherent weakness in each, namely the relatively large power consumption of a single chip CPU and the difficulty of reconfiguring a dedicated LSI circuit to perform different and/or additional functions.

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Tokyo, Japan

Masaaki Akahori