International Business Machines Corporation

Mary Joseph Saccamango

Jente Benedict Kuang

Louis L Hsu

Somnuk Ratanaphanyarat

Joseph F Shepard

Hyun J Shin

David C Ahlgren

Taqi Nasser Buti

Pong-Fei Lu

Shao-Fu S Chu

David A Sunderland

Rajiv V Joshi

Jack Oon Chu

Robert J Von Gutfeld

Tze-Chiang Chen

David Howard Allen

Ching-Te Kent Chuang

Fariborz Assaderaghi

Daniel Lawrence Stasiak

Paul Andrew Ronsheim

Shaw-Ning Mei

Martin Revitz

Mario M Pelella

Kyong-Min Kim

Ralph W Young

Giovanni Fiorenza

Donald R Vigliotti

Methods and apparatus are provided to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits. A select signal for the SOI CMOS circuit is received. A floating body charge monitoring circuit is coupled to the SOI CMOS circuit for monitoring excess body charges in at least one predefined SOI device and providing an output control signal. A select signal adjusting circuit is coupled to the floating body charge monitoring circuit receiving the output control signal and the select signal and providing a conditionally adjusted select signal responsive to the output control signal of the floating body charge monitor circuit. The conditionally adjusted select signal is applied to the SOI CMOS circuit. The conditionally adjusted select signal provided by the select signal adjusting circuit responsive to the output control signal of the floating body charge monitor circuit includes a predefined delay at the trailing edge of the select signal extending the select signal pulse width. The conditionally adjusted select signal includes a shortened select signal pulse having a predefined delay at the rising edge of the select signal. The conditionally adjusted select signal includes a substantially unchanged select signal pulse width with a predefined delay of the rising edge of the select signal.

Method and apparatus to ensure functionality and timing robustness in SOI circuits

The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.

Method and system for improving the performance on SOI memory arrays in an SRAM architecture system

A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.

Method and apparatus for enhanced SOI passgate operations

Methods and apparatus are provided for monitoring excess body charges in partially depleted SOI CMOS devices. An apparatus for floating body charge monitoring in partially depleted silicon-on-insulator (SOI) CMOS circuits includes a monitor core circuit for conditionally generating an intentional bipolar discharge current. A current mirroring multiplier is coupled to the monitor core circuit for amplifying the intentional bipolar discharge current and generating a state disturb current. A state setting latch is coupled to the current mirroring multiplier for determining and setting a condition for a discharge action.

Floating body charge monitor circuit for partially depleted SOI CMOS technology

In a method and apparatus for reducing parasitic bipolar current in an insulated body, field effect transistor (&ldquo;FET&rdquo;), for an n-type FET, the body of the insulated body NFET is electrically isolated, responsive to turning on the NFET. This permits a charge to accumulate on the body in connection with turning the NFET on, temporarily lowering the threshold voltage for the insulated body NFET. Responsive to turning off the insulated body NFET, at least a portion of the charge on the body is discharged. This discharging of the body reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off. For a p-type FET that is susceptible to parasitic bipolar current, the body is discharged responsive to turning off the PFET, and isolated responsive to turning on the PFET.

Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor

Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.

Method of discharging SOI floating body charge

SOI floating body charge monitor circuit and method

An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.

Ramp-up rate control circuit for flash memory charge pump

A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

Discharge circuit in a semiconductor memory

A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

Thin film transistor with self-aligned bottom gate

A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

Method for making heterojunction bipolar transistor with self-aligned

Method of making thin film transistor with a self-aligned bottom gate

A thick-oxide ESD transistor for a BiCMOS integrated circuit has its source/drain contacts formed of the BiCMOS base or emitter polysilicon and its source/drain formed by an outdiffusion of the respective polysilicon contact. In one embodiment the BiCMOS resistor doping deepens the ESD source/drains, and in another embodiment the BiCMOS collector reach through doping deepens the ESD source/drains. The entire ESD transistor is fabricated from a standard BiCMOS process without any additional steps, has an area of about 100 square microns, can shunt up to 6000 volts, and has a turn-on time of about 10 picoseconds.

Electrostatic discharge protection device

An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Image reversal process for self-aligned implants in planar

An inexpensive and reliable technique for forming connections to a substrate or buried layer of a semiconductor structure employs a laser to melt a small, selected region of a lightly doped layer and a highly doped underlying layer. Extremely rapid diffusion of impurities and mixing of materials within the liquid phase of the melt quickly creates a uniformly doped conductive region when the melt is allowed to recrystallize.

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Poughquag, NY, United States of America

Mary Joseph Saccamango