Texas Instruments Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Mary Drummond Roby

Stuart M Jacobsen

Daniel Joseph Vitkavage

Steven Alan Lytle

Erika Leigh Shoemaker

Maria Wang

Robert Alan Ashton

John Michael Sharpe

Morgan J Thoma

Matthew Moucheron

Jerome Chu

Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.

Process for reactive ion etching a layer of diamond like carbon

Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Semiconductor device including an amorphous nitrided silicon adhesion layer and method of manufacture therefor

A thermal inkjet printheadof the present invention includes a heating element, an ink chamber, control circuitry, an ink reservoir, and a memory array. The control circuitrycauses the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory arraystores and provides the identification parameters for the thermal inkjet printhead. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like. The identification parameters can include other information such as a unique serial identification number for the thermal inkjet printhead, manufacturer serial number, lot number, date of manufacture, compatible printers, ink capacity, ink remaining, re-ordering information for replacement ink cartridges, and the like.

Inkjet printhead incorporating a memory array

The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.

Process for the selective control of feature size in lithographic processing

The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof

A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.

Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies

The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.

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Orlando, FL, United States of America

Mary Drummond Roby