International Business Machines Corporation

Government of the United States of America, As Represented by the Secretary of Commerce

Mary Beth Rothwell

Jerry M Chow

James Robert Rozen

David William Abraham

George Andrew Keefe

Jay Michael Gambetta

Roy Rongqing Yu

Matthias Steffen

Antonio D Corcoles Gonzalez

Eric Andrew Joseph

James J Bucchignano

Ghavam G Shahidi

Josephine B Chang

Christian Lavoie

Hariklia Deligianni

Gareth Geoffrey Hougham

John Michael Cotte

Lubomyr Taras Romankiw

Chad Tyler Rigetti

Qiang Huang

Stuart S P Parkin

John Patrick Hummel

Gerald Warren Gibson, Jr

Ronald Wayne Nunes

Peter M Fryer

Chung H Lam

Sampath Purushothaman

Alejandro Gabriel Schrott

Matthew Joseph Breitwisch

Sarunya Bangsaruntip

Bipin Rajendran

Chang Chyi Tsuei

David P Pappas

David S Wisbey

Jiansong Gao

Dustin A Hite

Michael R Vissers

Robert Luke Wisneiff

Roy Rongquing Yu

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.

Bump bonded cryogenic chip carrier

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.

A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.

Modular array of vertically integrated superconducting qubit devices for scalable quantum computing

A method for adjusting a qubit includes measuring a qubit characteristic of a qubit device and computing a modification to correct the qubit characteristic. A geometry of a shunt capacitor is adjusted using a laser direct write process. The qubit characteristic is verified.

Qubits by selective laser-modulated deposition

A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.

Suspended superconducting qubits

A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate.

Removal of spurious microwave modes via flip-chip crossover

A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

Chip mode isolation and cross-talk reduction through buried metal layers and through-vias

Method of fabricating a coplanar waveguide device including removal of spurious microwave modes via flip-chip crossover

A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.

Growing community of inventors

Ridgefield, CT, United States of America

Mary Beth Rothwell