Altera Corporation

Marwan A Khalaf

David Wolk Mendel

Bruce B Pedersen

Francis B Heile

David Karchmer

Jimmy Lawson

Michael Menghui Zheng

Renxin Xia

Allan Thomas Davidson

Neville Carvalho

Daniel Bowersox

Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

Method and system for partial reconfiguration simulation

A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Digital phase detection circuit and method

A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of programmed devices whose logic functions have been proven and need not change, but which operate in an environment that changes, necessitating different characteristics, without having to redesign the programming metallization layers, and therefore without involving the device manufacturer. The programmable elements may include input/output elements, which may need adjustment because the signal characteristics of the larger system change, or clock circuitry, which may need adjustment because environmental conditions such as changes in the expected operating temperature may affect clock signals in the larger system.

Mask-programmable logic device with programmable portions

A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a &ldquo;sub-netlist&rdquo; within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

Generation of sub-netlists for use in incremental compilation

A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a 'sub-netlist' within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

Growing community of inventors

San Carlos, CA, United States of America

Marwan A Khalaf