International Business Machines Corporation

Marvin Von Der Ehe

Manuel Beck

Florian Braun

Lukas Dällenbach

Heinz Josef Hemmes

Jesse Peter Surprise

Semiconductor device design automation by receiving an initial semiconductor design, identifying scannable cells according to the semiconductor design, determining scannable cell locations, identifying a cluster of scannable cells among the scannable cells according to the locations, forming a scan chain configured to connect at least some of the scannable cells of the cluster, identifying a scan chain cluster including the scan chain logical connections; and generating a scan chain scan-multiplexer location for scan chain clusters.

Designing semiconductor circuit test elements

A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Placement and timing aware wire tagging

There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

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Herrenberg, Germany

Marvin Von Der Ehe