Macom Technology Solutions Holdings, Inc.

Wolfspeed, Inc.

Infineon Technologies Ag

Cree Gmbh

Marvin Marbell

Basim H Noori

Qianli Mu

Kwangmo Chris Lim

Alexander Komposch

Scott Thomas Sheppard

Jeremy Fisher

Haedong Jang

Michael E Watts

Madhu Chidurala

Mario Bokatius

Jangheon Kim

Bill Agar

Michael Lefevre

Jonathan Chang

Richard Wilson

Daniel Namishia

Dan Namishia

Donald Farrell

Ulf Andre

Simon Ward

Kenneth P Brewer

Arthur Pun

Sonoko Aristud

E J Hashimoto

Niklas Thulin

Ej Hashimoto

Dan Etter

Melvin Nava

Daniel Etter

Michael Devita

A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.

Transistor amplifier with PCB routing and surface mounted transistor die

A transistor amplifier includes a die comprising a gate terminal, a drain terminal, and a source terminal, a circuitry module on the transistor die and electrically coupled to the gate terminal, the drain terminal, and/or the source terminal, and one or more passive electrical components on a first surface of the circuitry module. The one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor amplifier and/or between the drain terminal and a second lead of the transistor amplifier.

RF amplifier devices and methods of manufacturing including modularized designs with flip chip interconnections

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

IPD components having SiC substrates and devices and processes implementing the same

A component includes a substrate board; a thermal bridge structured and arranged on the substrate board, where the thermal bridge is configured to transfer heat from the substrate board including an area adjacent to or on a hotspot of the substrate board; where the thermal bridge is configured to transfer the heat to another location on the substrate board for removal of the heat from the substrate board; and where the thermal bridge may include silicon carbide.

Silicon carbide thermal bridge integrated on a low thermal conductivity substrate and processes implementing the same

An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed.

Stacked RF circuit topology

A transistor device includes a metal submount; a transistor die arranged on said metal submount; a first integrated passive device (IPD) component that includes a first substrate arranged on said metal submount; and a second integrated passive device (IPD) component that includes a second substrate arranged on the metal submount. Additionally, the first substrate is a different material from the second substrate.

Multi-typed integrated passive device (IPD) components and devices and processes implementing the same

A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

RF amplifier devices including top side contacts and methods of manufacturing

RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

Group III nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias

A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.

Packaged RF power device with PCB routing outside protective member

A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.

Device having a coupled interstage transformer and process implementing the same

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

RF amplifiers having shielded transmission line structures

A semiconductor device package includes a plurality of input leads, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combined output lead configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal.

Output-integrated transistor device packages

A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.

Output-integrated transistor amplifier device packages incorporating internal connections

A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.

Growing community of inventors

Morgan Hill, CA, United States of America

Marvin Marbell