Westinghouse Electric Corporation

Other

Eastman-kodak Company

United States of America As Represented by the Secretary of the Air Force

Northrop Grumman Systems Corporation

Marvin H White

Donald R Lampe

Hung C Lin

James H Mims

Ingham A Mack

Robert A Frosch

Francis J Kub

Constantine N Anagnostopoulos

John L Fagan

James R Cricchi

Patrick Bruckner Shea

Kenneth J Petrosky

Joseph Terence Smith

Richard R Siergiej

Arthur S Jensen

Charles D Brandt

David H McCann

Franklyn C Blaha

Dennis Allen Adams

Alfred P Turly

A photovoltaic semiconductor solar cell with a backside semiconductor-oxide-nitride-oxide nonvolatile charge storage structure (referred to as a 'PHONOS solar cell') is disclosed. The PHONOS solar cell includes a semiconductor surface region, a semiconductor bulk region, and a backside structure that includes the SONO nonvolatile charge storage structure and a backside contact. The backside SONO nonvolatile charge storage structure greatly improves solar cell efficiency gains by eliminating 'backside' losses, i.e., losses due to the recombination of photo-generated minority charge carriers created by the incident sunlight. The PHONOS solar cell is a highly efficient, ultra-thin, semiconductor solar cell that can be manufactured at low cost.

Photovoltaic silicon solar cells

A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Non-volatile random access memory cell constructed of silicon carbide

A CCD image sensor has a plurality of elements, each such sensing element includes a doped semiconductor substrate, an insulator layer over the semiconductor substrate, and an electrode on the insulator layer which when potential is applied to the electrode creates a well in the bulk of the substrate which collects charge as a result of a photoelectric process. The insulator layer has a thin portion selected so as to allow excess charge collected in the channel to tunnel through the thin region to the electrode and thereby prevent blooming.

Blooming control in CCD image sensors

An adaptive analog processor incorporating a analog shift register having a plurality of taps, multipliers at each tap for multiplying the tap value times a weight value, a first adder for summing the output of the multipliers, a second adder for subtracting the output of the adder from a second analog signal, means for incrementing the weights in response to the magnitude and polarity of the error signal and the polarity of the data signal. The invention overcomes the problem of building monolithic multitap adaptive filters utilizing the clipped-data least mean square error algorithm.

Adaptive analog processor

A charge control circuit for bidirectionally transferring metered amounts of charge, selectively, through a transfer channel of a four gate electrode charge coupled device (CCD) is disclosed. The bidirectional charge control circuit is used primarily to increment and decrement metered amounts of charge respectively to and from a charge storage medium. More specifically, five electrical signals are generated to have varying potentials in accordance with predetermined time sequences. These signals are applied to the four gate electrode CCD in a selected one of two states to either increment or decrement a metered amount of charge therethrough to or from the charge storage medium respectively, in a predetermined number of five segments. One of the generated signals governs the metering of charge for each increment or decrement operation.

Bidirectional charge control circuit

An imaging system comprising a multi-channel matrix array of CCD devices wherein a plurality of sensor cells (pixels) in each channel are subdivided and operated in discrete intercoupled groups or subarrays with a readout CCD shift register terminating each end of the channels. Clock voltages are applied to the subarrays and are manipulated to selectively cause charge signal flow in each subarray in either direction independent of the other subarrays. More particularly, the array is divided into six independent subarrays, three on each side of the array, such that each channel common to three subarrays is divided into three sections of three sensor cells each. By selective application of four phase clock voltages, either one, two or all three of the sections cause charge signal flow in one direction, while the remainder cause charge signal flow in the opposite direction. This creates a form of selective electronic exposure control which provides an effective variable time delay and integration of three, six or nine sensor cells or integration stages. The device is constructed on a semiconductor sustrate with a buried channel and is adapted for front surface imaging through transparent doped tin oxide gates.

Time delay and integration detectors using charge transfer devices

Apparatus for forming one or more sonar beams in response to acoustic energy received by a transducer array. To minimize volume utilization, a plurality of CCD's are formed on an integrated circuit chip with the CCD's being of progressively smaller length. Half of the CCD array is folded over to match the other half so that each CCD has an opposing CCD with both CCD's propagating a signal toward a common output diode. By providing one integrated circuit chip for each desired beam with appropriately different clocking frequencies multiple beams may be formed, and with the provision of a variable clocking frequency, one or more beams may be steered. Transversal filter operations may also be performed by the apparatus.

CCD Signal processor

An analog multiplier for multiplying the signals derived from a charge coupled device (CCD) tap includes a balanced multiplier of a first conductivity-type and a buffer of a second conductivity-type coupled between the CCD tap and the balanced multiplier. The multiplier includes first and second transistors, the drains of which are coupled together to form an input. The buffer includes a load transistor coupled to the output of an amplifying transistor. Means are included for coupling the output of the amplifier transistor and the multiplier input.

CMOS Analog multiplier for CCD signal processing

An addressable MNOS transistor structure is disclosed employing a plurality of gate regions between the source and drain diffusion regions of each transistor cell. The transistor cell is characterized by high and low threshold states which are settable by selective actuation of the corresponding plurality of gate regions. Reading of the state of the transistor is accomplished by applying a read voltage, having a value intermediate the two threshold values, to the corresponding plurality of gate regions and measuring whether or not an applied charge discharges from one diffusion region to the other.

Addressable MNOS cell for non-volatile memories

A stabilized charge injector for charge coupled devices (CCD) includes a diffusion and two or more gate structures in a CCD channel wherein the diffusion alternately acts as a source and drain of the minority-type signal carriers. D.C. signals are applied to the gates immediately adjacent the diffusion and the next successive adjacent gate to provide a charge injection which is proportional to the difference between the signal voltage applied to the one of the two gates and a DC reference voltage applied to the other thereof. Low noise performance is achieved through utilization of a quasi-static operation in which neither of the aforementioned gates adjacent the diffusion is pulsed. Moreover, the use of a gate injector presents at the input, a true capacitance defined as a function of the gate oxide layer. Hence, the value of capacitance is constant and independent of the signal voltage applied. A stabilized charge injector structure is disclosed providing a large value of capacitance for minimizing noise in the injection operation, and wherein problems otherwise arising out of the large size of the capacitance as to adequate speed of propagation of charges from the capacitance to a CCD charge transfer structure are overcome by special gate electrode structures and pulsing techniques to provide successive pushes of the charge being injected from the gate capacitance into the receiving CCD transfer device. The stabilized charge injector may be used for either serial or parallel injection into a CCD channel and its advantages most fully being realized in the parallel input mode; operating waveforms for the charge injector to provide parallel injection into a CCD channel during each shift cycle thereof and, alternatively, to provide selectively timed parallel charge injection in successive intervals are disclosed.

Stabilized charge injector for charge coupled devices with means for

A method and apparatus for charge addressing a non-volatile MNOS memory cell in a LSI array of memory cells, is disclosed. Each MNOS cell of the array is made up of a substrate; adjacent diffusion areas in the substrate; a memory window intermediate the adjacent diffusion areas, controlled by a memory gate; and an enable gate adjacent the memory window and overlapping one of the diffusion areas. The memory gate and the enable gate are each separated from the substrate and each other by silicon dioxide/silicon nitride layers to provide a capacitive dielectric. Addressing of an individual cell in the array is achieved by selective activation of a corresponding enable gate and a corresponding memory gate, which are formed in an orthogonal grid array. The cell is accessed by a single stage of a shift register for both read and write operations through a transfer gating means.

Method and apparatus for addressing a non-volatile memory array

The proposed general-purpose, fully-analog device is capable of such functions as auto-correlation, cross-correlation, convolution, transversal filters, etc. at high speeds (one megahertz typical sample rates) with no analog-to-digital or digital-to-analog conversions. The device correlates analog samples in one CCD channel against analog samples in a second CCD channel by means of balanced MOSFET's which multiply the associated voltage samples to give current products that are summed for all multipliers. The two CCD channels include unique floating-clock sensor and buffer circuits which sense the CCD charge samples without affecting the efficiency of their propagation along the CCD shift register. The matched MOSFET multipliers and current summing amplifiers are also uniquely combined in a dual-differential configuration so as to minimize the nondestructive sensing and buffering cells and the matched multiplier cells with the longitudinal dimensions of the CCD, permitting the latter to be small for efficient propagation.

Dual-CCD, real-time, fully-analog correlator

A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to each of the element sensors of the corresponding column of the array. Two 'snapshots' of the scene are taken at time-displaced intervals and are compared to detect differences therebetween to eliminate background, or unchanging scene content. The individual sensors provide outputs which are injected into the .alpha. stages of the corresponding paired shift register stages of each CCD shift register in a first time interval corresponding to the first 'snapshot'. The resulting charge packets in the first (.alpha.) stages then are advanced to the second (.beta.) stages of each shift register pair. The second 'snapshot' corresponds to injecting a second signal into the .alpha. stages of the plurality of pairs of .alpha., .beta. stages. The CCD shift registers then are read out simultaneously and in succession as to the plural, related .alpha., .beta. pairs of stages containing the time-displaced elemental signal samples. A further CCD shift register including a number of .alpha., .beta. pairs of stages receives the parallel .alpha., .beta. outputs in corresponding time sequential manner to maintain the .alpha., .beta. related pair arrangement of the time-displaced elemental samples. An output circuit compares the .alpha., .beta. signals for each elemental area and determines the difference therebetween. A CRT display receives the difference signal outputs for displaying moving target information.

CCD focal plane processor for moving target imaging

An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

Drain source protected MNOS transistor and method of manufacture

An N-channel MOS transistor wherein two layers of different dielectric materials (e.g., silicon dioxide and silicon nitride) are used in conjunction with a P-doped silicon gate to permit the use of a higher resistivity P-type substrate. This enables a higher junction breakdown voltage and a higher threshold voltage without a reverse bias on the substrate due to an increase in the work function difference between the gate and substrate. Because of the lower concentration (i.e., higher resistivity) of the substrate, high frequency response is increased due to lower drain-source capacitance.

Growing community of inventors

Laurel, MD, United States of America

Marvin H White