Cadence Design Systems, Inc.

Marut Agarwal

Naresh Kumar

Umesh Gupta

Rakesh Agarwal

Ankit Sethi

Shubham Kumar

Prashant Sethia

Satyendra Patel

The present disclosure relates to a system and method for electronic design automation. Embodiments may include loading one or more libraries, netlists, or constraints associated with an electronic design and loading parasitic data associated with the electronic design. Embodiments may further include performing a self adaptive, infinite depth, path based analysis on at least a portion of the electronic design. Embodiments may also include analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis.

Adaptive path based analysis process

A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

IPBA-driven full-depth EPBA of operational timing for circuit design

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Ghaziabad, India

Marut Agarwal