Advanced Micro Devices Corporation

Globalfoundries Inc.

Cypress Semiconductor Corporation

Cryptography Research, Inc.

Marufa Kaniz

Somnath Viswanath

Jeffrey Roy Dwork

Robert Alan Williams

Mohammad Y Maniar

Scott C Best

Chandan Egbert

Bryan Jason Wang

Michael Achter

Evrim Binboga

Winthrop Wu

Chin-Wei Kate Liang

Guilherme Ozari De Almeida

Kevin Pond, Legal Representative

Murni Mohd-Salleh

A request to perform a memory operation addressed to a first address corresponding to a first logical unit of logical units of a memory is received. Address mask data that corresponds to the logical units is identified. Multiple transformed addresses are determined using the first address and the address mask data. The transformed addresses can include a target address corresponding to the first logical unit and additional addresses corresponding to other logical units. The memory operation is performed at the target address corresponding to the first logical unit and dummy memory operations are performed at the additional addresses corresponding to the additional logical units.

Obfuscation of data in a memory

A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Pipelining in a memory

The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.

Two parallel engines for high speed transmit IPSEC processing

Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.

Network interface systems and methods for offloading segmentation and/or checksumming with security processing

A system includes a plurality of network devices and an external memory. Each network device includes an address table. The external memory includes a group of address tables corresponding to the address tables of the network devices. The system monitors the address table associated with each of the network devices, detects whether one of the address tables has been updated, and updates the corresponding address table in the external memory in response to detecting an update to one of the address tables.

System and method for implementing an IRC across multiple network devices

A network interface system is presented for interfacing a host system with a network, including a bus interface system, a media access control system, a memory system, a security system, and a descriptor management system, wherein the descriptor management system obtains initialization vector information from the host system and provides the initialization vector information to the security system. A method of encrypting outgoing data in a network interface system is provided, comprising providing initialization vector information from a descriptor to a security system in a network interface system, selectively encrypting or authenticating outgoing data using the security system, and selectively employing an initialization vector from the outgoing data to perform CBC encryption of the outgoing data according to the initialization vector information.

Methods and apparatus for passing initialization vector information from software to hardware to perform IPsec encryption operation

Two parallel engines for high speed transmit IPsec processing

A security association architecture system of the present invention facilitates network data transfer by providing an internal portion of a security association database that can be quickly accessed to obtain security associations as well as an external component that stores the complete security association database. As a result, at least some security associations for incoming received frames and outgoing transmitted frames can be obtained from the internal portion located on a network interface device without accessing system memory, a host computer, and the like in order to obtain the security associations to perform security processing.

Security association table lookup architecture and method of operation

One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The security system selectively perform security processing on data incoming from the network based on security associations stored in a memory external to the network interface system, typically a host system memory. The security association for any given frame, when available, is fetched from the external memory after the frame begins to arrive in the network interface system based in part on information contained in the frame. Preferably, the fetch begins before the frame is fully received and the security association is queued whereby security processing can begin without having to wait for the security association to be fetched.

Network interface with security association data prefetch for high speed offloaded security processing

An address lookup table in a multiport switch is implemented as a plurality of address sub-tables. Entries in the address sub-tables are stored at row addresses based on a hash of the information in the entry. Hash collisions are stored in a common heap as a linked list of chained values. Entries in the address sub-tables at any particular address are alternated between the address sub-tables. A search of the address sub-table for the particular entry is performed simultaneously on the plurality of address sub-tables. In this manner, the total memory size of the address table can be increased relative to a single address sub-table while decreasing the length of the longest chain length and the length of the average chain length.

Alternately accessed parallel lookup tables for locating information in a packet switched network

An address lookup table in a multiport switch is implemented as a plurality of address sub-tables. Entries in the address sub-tables are stored at row addresses based on a hash of the information in the entry. Entries in the address sub-tables are stored in one of the address sub-tables, as determined by pre-selected information relating to the entry. For example, the least significant bit of a source or destination MAC address may be used to select between two address sub-tables. In this manner, the total memory size of the address table can be increased relative to a single address sub-table while decreasing the length of the longest chain and the length of the average chain.

Parallel lookup tables for locating information in a packet switched network

A multiport device includes an internal rules checking (IRC) circuit that makes frame forwarding decisions for frames received from a network. The IRC circuit includes multiple frame lookup components implemented in parallel. More particularly, each of the multiple frame lookup components includes a source address lookup component and a destination address lookup component, and an address table. The source address lookup component and the destination address lookup component accesses the address table to determine the correct forwarding information for a frame. If an address is not present in the table, a source address learning component updates the table. The source address learning component may be shared by each of the multiple frame lookup components.

Multiple address lookup engines running in parallel in a switch for a packet-switched network

A multiport device includes an internal rules checking (IRC) circuit that makes frame forwarding decisions for frames received from a network. The IRC circuit includes multiple frame lookup components implemented in parallel. More particularly, each of the multiple frame lookup components includes a source address lookup component and a destination address lookup component. The source address and the destination address lookup component of the multiple frame lookup components accesses a common address table to determine the correct forwarding information for a frame. If an address is not present in the table, a source address learning component updates the table. The source address learning component may be shared by each of the multiple frame lookup components.

Single address lookup table with multiple address lookup engines running in parallel in a switch for a packet-switched network

An integrated device includes an external memory interface that includes address decoding logic configured for identifying a destination device register based on register address information retrieved from an external memory. The external memory interface, upon identifying the destination device register, loads the destination device register with register data read from the external memory, for example contiguously following the corresponding register address information. Hence, the integrated device can be programmed on a per register basis, without the necessity of an EEPROM map.

Growing community of inventors

Santa Clara, CA, United States of America

Marufa Kaniz