Nxp Usa, Inc.

Freescale Semiconductor,inc.

Maruf Ahmed

Joseph Staudinger

Hussain Hasanali Ladhani

Margaret A Szymanowski

Doherty power amplifiers (DPAs), and related circuits, devices, systems and methods of operation, are disclosed herein. In an example embodiment, a system includes a first transistor device operable as a carrier amplifier, a second transistor device operable as a peaking amplifier, and at least one first integrated passive device (IPD) coupled between a combining node and each of carrier and peaking amplifier output ports. The system includes a first frequency-corrective network coupling the carrier amplifier output port with the node, where the network is formed at least in part by the at least one first IPD and is configured to operate as a first quasi-inverter network that includes a low-pass network. Additionally, the system includes a second frequency-corrective network coupling the peaking amplifier output port with the node, where the network is formed at least in part by the at least one first IPD and includes a bandpass network.

Combiner circuit for Doherty power amplifier and related method of operation for achieving enhanced radio frequency and video bandwidth

An amplifier device includes an input terminal, an output terminal, a first transistor having a control terminal and first and second current-carrying terminals, and a class-J circuit coupled between the second current-carrying terminal of the first transistor and the output terminal and configured to harmonically terminate the first transistor. The class-J circuit may include a first resonator, characterized by a first resonant frequency substantially equal to a second harmonic frequency. The first resonator may be coupled between the second current-carrying terminal and a voltage reference. A shunt inductor that is distinct from the first resonator may be coupled between the second current-carrying terminal and the voltage reference.

Amplifier device with harmonic termination circuit

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

Phase correction in a Doherty power amplifier

The embodiments described herein provide inverse class F (class F) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier.

Growing community of inventors

Tempe, AZ, United States of America

Maruf Ahmed