U.S. Philips Corporation

Martinus P Versleijen

Ronald Dekker

Henricus G Maas

Dirk J Gravesteijn

The invention relates to a method of manufacturing a semiconductor device (1) for surface mounting. Such a method is known, whereby such a semiconductor device is manufactured in that a semiconductor body with a semiconductor element is mounted on a metal lead frame with metal package leads, after which contact surfaces of the semiconductor element are connected to the package leads by means of bonding wires. It is found that semiconductor devices of small dimensions are difficult to realize by this known method, while in addition the manufacture of integrated circuits with very many package leads is comparatively expensive owing to the many connections which are to be made between the integrated circuits and the package leads. According to the invention, the semiconductor devices are packaged while they are still on a slice of semiconductor material, while the package leads are formed from the semiconductor material. In the method according to the invention, the semiconductor devices are manufactured without the necessity of a lead frame, bonding wires, or metal package leads. Thanks to the IC technologies at the wafer level, such as photolithography, etching, etc., the method according to the invention renders possible semiconductor devices of very small dimensions. In addition, integrated circuits with very many package leads can be manufactured in a simple manner without additional steps being necessary. The method according to the invention is thus comparatively inexpensive.

Method of manufacturing a semiconductor device for surface mounting

A semiconductor device includes a semiconductor body (1) having a semiconductor element with connection points (2, 3) which adjoins a surface (4) of the semiconductor body (1) and is laterally insulated and surrounded by a first depression (5) in the surface (4), which depression (5) is provided with a wall (6) and a bottom (7), while the surface (4) of the semiconductor body (1) and the wall (6) and bottom (7) of the depression (5) are covered with an insulating layer (8). The connection points (2, 3) are provided in the insulating layer (8) on the surface (4) of the semiconductor body (1) and are connected to conductor tracks (10, 11) which connect the connection points (2, 3) across a wall (6) to connection surfaces (12, 13) associated with the connection points (2, 3) and situated on the bottom (7). It is found in practice that, in the case of progressive miniaturization, the manufacture of such devices leads to rejects caused by short-circuits between connection surfaces (12, 13). According to the invention, one or several further depressions (50) surrounded by the first depression (5) is/are present in the surface (4) of the semiconductor body (1), while only one connection surface (12, 13) is present on the bottom (7, 57) of each of the first and further depressions (5, 50), which connection surface is connected to a connection point (2, 3) on the surface (4) of the semiconductor body (1) via a conductor track (10, 11). Short-circuits are found to take place in the known semiconductor devices on a wall (6) of the depression (5) when there are more than one conductor tracks (10, 11) on this wall (6). Here, however, only one conductor track (10 or 11) is present on the wall (6, 56 of the depression (5, 50), so short-circuits with other conductor tracks on the wall (6, 56) cannot arise.

Semiconductor device with a semiconductor element provided in a mesa

A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1). According to the invention, a depression (4) is provided in this main surface (3), cutting through the emitter region (12) of the first transistor (T1) which at the same time is the collector region (12) of the second transistor (T2), the space charge region (13), and the base region (14) of the second transistor (T2) and laterally bounding these; regions, while a connection electrode (B1) for the base region (11) of the first transistor (T1) is provided in the depression (4). No latch-up by a parasitic transistor then takes place in the device.

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Eindhoven, Netherlands

Martinus P Versleijen