Takumi Technology Corporation

Applied Materials, Inc.

Sage Design Automation Ltd

Np Komplete Technologies B.v.

Martinus Maria Berkens

Nitin K Ingle

Arvind Sundarrajan

Suketu Arun Parikh

Guan Huei See

Andrew W Yeoh

Sameer Deshpande

Ashish Pal

Yen-Chu Yang

El Mehdi Bazizi

Balasubramanian Pranatharthiharan

Anurag Mittal

Simon Johannes Klaver

A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.

Self-aligned wide backside power rail contacts to multiple transistor sources

A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L) comprising one or more polygon shapes (P) defined by a plurality of polygon parameters (W,H). Design rules (R,R) are received comprising inequality constraints (C) on the polygon parameters (W,H). A second layout (L) is calculated by applying a random change (&#x394;W) of value to at least one of the polygon parameters (W) of the first layout (L). A third layout (L) is calculated by varying values of the polygon parameters (W,H) of the second layout (L) until a respective slack (S,S) of the polygon parameters (W,H) with respect to one or more of the parameter boundaries (B,B) defined by the constraints is minimized. The third layout (L) may be stored as candidate test layout.

Automation generation of test layouts for verifying a DRC deck

There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit partas seed points, projecting a specifically designed polygon shapeproximal to a seed pointand calculating an overlap areabetween the projected polygon shapeand a second circuit part. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.

Rule checking

The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number. Polygon patterns are identified as predefined complex circuit elements and wherein the cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit design intent. The cost number functions can further have interdependencies in multiple critical dimensions of the polygon patterns so as to take the two dimensional nature into account.

Method of selecting a set of illumination conditions of a lithographic apparatus for optimizing an integrated circuit physical layout

The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.

Method for optimizing an integrated circuit physical layout

Growing community of inventors

Eindhoven, Netherlands

Martinus Maria Berkens