Arm Limited

U-Blox Ag

Martinus Cornelis Wezelenburg

Thomas Kelshaw Conway

Johan Matterne

Dominic Hugo Symes

Antony John Penton

Daniel Kershaw

Jan Guffens

Jeremy Davies

Dirk Duerinckx

Koenraad Pieter Lodewijk Van Nieuwenhove

Ken Yi Wong

A data processing systemincludes an instruction decoderresponsive to polynomial divide instructions DIVL.Pto generate control signals that control processing circuitryto perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of '1' such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

Polynomial data processing operation

An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient.

Error correction for multilevel flash memory

An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P&#x2212;(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.

Error control coding for single error correction and double error detection

An encoder for generating check data to accompaning payload data uses parallel lane encoders each using a common encoder matrix. Mask circuitry applies mask values to the lane check data generated by the lane encoders. The mask circuitry generates check data for the K-bits of payload data. The mask values applied by the mask circuitry may be selected so as to bring about a re-ordering of the M-bit words.

Check data encoding using parallel lane encoders

A data processing apparatus has a main controller for executing a programmable sequence of instructions including a transaction sequence of instructions used to process a transaction to be initiated by the data processing apparatus. The transaction sequence of instructions is programmed dependent on the interconnect protocol. The data processing apparatus has an interconnect interface unit including a plurality of queues with at least one send queue for issuing outbound payload information to the interconnect circuitry, and at least one receive queue for receiving inbound payload information from the interconnect circuitry. An interface controller is provided for pushing the outbound payload information on to the at least one send queue and popping the inbound payload information from the at least one receive queue, under the control of commands issued by the main controller. The interconnect interface unit has an interconnect port for communicating with the interconnect circuitry.

Data processing apparatus and method for connection to interconnect circuitry

A data compressor for compressing a data signal and a corresponding data decompressor are disclosed. The data compressor comprises: compression circuitry for compressing said data signal using a plurality of variable length compression codes; a digital code select signal generator for generating a digital code select signal from an indicator signal indicative of a preferred compression distribution, a frequency of said digital code select signal being higher than a frequency of said indicator signal and an average value of said digital code select signal corresponding to an average value of said indicator signal; said compression circuitry being responsive to said digital code select signal to select between one of said plurality of compression codes in dependence upon a current value of said digital code select signal and to compress said data signal using said selected compression code.

Dynamic selection of suitable codes for variable length coding and decoding

A data processing system is provided comprising a main processor operable to perform a plurality of data processing tasks, a data engine having a data engine core operable to perform a number of said plurality of data processing tasks on behalf of said main processor and a data stream processing unit providing a data communication path between said main processing unit and said data engine core. The data stream processing unit has a control interface operable to receive from said data engine core at least one command and a data stream controller operable to receive at least one input data stream and to perform at least one operation on said at least one input data stream to generate at least one output data stream comprising a sequence of data elements. The data stream processing unit is responsive to said at least one command from said data engine core to control said data stream controller to perform said at least one operation.

Data processing system

A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic () has a plurality of functional units () configured to execute in parallel on data received from a data source. A decoder () is responsive to a single program instruction to control the data processing logic () to concurrently execute the single program instruction on each of a plurality of vector elements of each of a respective plurality of vector input operands () received from the data source using the plurality of functional units (). During execution of the single program instruction, the plurality of functional units () operate as a predetermined group on said plurality of vector elements () to perform at least a matrix-vector calculation in which the matrix is a non-identity matrix and entries of the matrix are one of:

Algebraic single instruction multiple data processing

A system and method for compiling a computer program comprising (a) performing a compilation generating an initial mapping of each code portion of the program in the memory; b) evaluating and generating a cost value associated with the initial mapping; c) if the cost value does not satisfy a threshold cost value, re-performing the compilation having regard to the record of each memory section; d) re-evaluating and generating a revised cost value associated with the modified mapping; e) iteratively repeating steps (c) and (d) until a predetermined condition is met; and f) outputting the mapping whose associated cost value most closely satisfied the threshold cost value. Such an approach enables a reduction in the power consumption resulting from memory accesses, reduces local memory requirements, and reduces the risk that size and complexity of the computer program will be constrained by the given local program memory size.

System and method for compiling a computer program

An interface requests instructions from a data store storing instructions of an application to be processed by a data processor, and receives and transmits the instructions to the data processor. The interface includes: an input that receives the instructions from the data store via at least one input bus; a buffer that stores received instructions; an output that outputs instructions to the data processing apparatus via the output bus; a control signal input that receives a control signal; and a buffer controller that controls the buffer to request an instruction subsequent to a previously received instruction within an instruction stream of the application from the data store in response to detection of no control signal on the control signal input and to detection of available buffer storage capacity. In response to a control signal received at the control signal input, the controller controls at least one of input and storage of instructions within the interface in order to seek to reduce instruction movement through the input.

Instruction stream control

A multi-dimensional FFT is calculated upon 2rows of 2data values set out end-to-end in memory by traversing the data set as a whole using stride values and block sizes which halve upon each pass through the data. As the data values represent multi-dimensional data, there are one or more dimensional boundaries within the data and as these are crossed the coefficient values being applied by the complex butterfly calculation are adjusted to take account of the manipulation being performed. The linearity of the matrix calculations underlying the butterfly calculation means that the order in which these calculations are performed is not significant and accordingly multiple passes with appropriate coefficient changes can perform a multi-dimensional calculation even if the different components of the calculation in respect of each dimension arise upon different passes through the data set.

Multi-dimensional fast fourier transform

A local FIFO memoryis provided within a local RAM memoryto provide access to source data values. A local controllermanages the asynchronous fetching of source data values to the local FIFO memoryand the optional writing back of these data values after processing to a source/sync memory. One or more local head pointers and one or more local tail pointers are used by the local memory controllerto manage storage within the local FIFO memorywhich is configured as a circular buffer; The remaining space within the local RAMmay be used for further data and the partitioning between FIFO operation and further data storage is programmable such that the same memory storagecan be used for multiple purposes as required.

Growing community of inventors

Leuven, Belgium

Martinus Cornelis Wezelenburg