Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V.

First Sensor Ag

Technische Unversität Berlin

Martin Wilke

Kai Zoschke

Hans-Hermann Oppermann

Thomas Fritzsch

Stephan Dobritz

Marc Schillgalies

Tolga Tekin

Hermann Oppermann

Michael Pierschel

Michael Töpper

Charles-Alix Manier

Ruben Chavez

Markus Wöhrmann

Oswin Ehrmann

Sabine Friedrich

Robert Gernhardt

Iman Sabri Alirezaei

A photosensitive element includes a semiconductor substrate, a light sensitive region formed in the semiconductor substrate, an inactive region at least partly surrounding the light sensitive region, and a protective layer having an opening leaving the light sensitive region uncovered by the protective layer. The protective layer is an anti-reflective coating having in at least a part of a spectral range between 300 nm and 1200 nm a reflectivity of less than 10% and a transmittance of less than 0.1%.

Photosensitive element and optoelectronic component

An arrangement for an optoelectronic component includes a substrate and an optical semiconductor chip arranged on the substrate. The optical semiconductor chip has an optically active region, a first optically non-active region, and a second optically non-active region. A connection structure connects a chip-side electrical connection to the optically active region. An electrical connection connects the chip-side electrical connection to a second substrate-side electrical connection. A coating is provided in a layer stack in the optically active region, in the first optically non-active region, and in the second optically non-active region. The layer stack includes a first layer and a second layer arranged above the first layer. The chip-side electrical connection and the connection structure in the first optically non-active region and the protective layer in the second optically non-active region are each arranged between the first layer and the second layer.

Arrangement for an optoelectronic component, manufacturing process and optoelectronic component

A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

Method for manufacturing a semiconductor component and a semiconductor component

A method for manufacturing metal structures for the electrical connection of components comprises the following steps: depositing an auxiliary layer on a substrate; structuring the auxiliary layer in a manner such that the substrate is exposed at least one environment which is envisaged for the metal structures; depositing a galvanic starting layer on the structured auxiliary layer; depositing a lithography layer on the galvanic starting layer and structuring the lithography layer in a manner such that the galvanic starting layer is exposed at least one location envisaged for the metal structure; galvanically depositing the at least one metal structure at the at least one exposed location; removing the structured auxiliary layer. An electronic component is also described.

Method for manufacturing a contact bump by thermal expansion of a patterned sacrificial layer underneath a galvanic layer

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Berlin, Germany

Martin Wilke