Intel Corporation

Martin Weiss

William T Blanton

Apratim Dhar

Tahir Ghani

Paul B Fischer

Biswajeet Guha

Charles Henry Wallace

Mauro J Kobrinsky

Leonard P Guler

William Hsu

Ruth Amy Brain

Brennen Karl Mueller

Ming-Chuan Yang

Michael Harper

Chytra Pawashe

Daniel Pantuso

Myra McDonnell

David Fryer

Shannon Daviess

Brian Kinnear

Telly Koffas

Kirsten H Thompson

Lance C Hibbeler

Aaron M White

James F Bondi

John H Irby, Iv

Benedict A Samuel

Bob Bigwood

Stefan Dickert

Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

Fabrication of gate-all-around integrated circuit structures having adjacent island structures

Embodiments disclosed herein include a lithography reticle set and methods of using such reticle sets. In an embodiment, the set comprises a first reticle and a second reticle. In an embodiment, the first reticle comprises a first grating having a first pitch, and a second grating having a second pitch. In an embodiment, the second reticle comprises a third grating having a third pitch, wherein the third pitch is different than the first pitch, and a fourth grating having a fourth pitch, wherein the fourth pitch is different than the first pitch. In an embodiment the third grating overlaps the first grating and the fourth grating overlaps the second grating when two or more edges of the first reticle are aligned with two or more edges of the second reticle. In an embodiment the first reticle or the second reticle further comprises a pattern recognition feature.

Image-based overlay targets incorporating features for pattern recognition and moire fringe patterns for measurement

Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.

Wafer to wafer bonding with low wafer distortion

Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer.

Winged vias to increase overlay margin

In one embodiment, a wafer alignment system, comprises a radiation source to generate radiation, a radiation directing assembly to direct at least a portion of the radiation onto a surface of a wafer, the radiation having a polarization state, an optical analyzer to collect at least a portion of the radiation reflected from the wafer, the wafer including at least a first region having a first grating pattern oriented in a first direction and at least a second region having a second grating pattern oriented in a second direction, different from the first direction.

Wafer level alignment structures using subwavelength grating polarizers

Pattern recognition targets including regions of one or more layers of gratings are used for semiconductor fabrication wafer alignment. Grates of the gratings are below the resolution limit of the alignment microscopes, and have dimensions compatible with design rules applied to actual device circuitry. Targets may be located by the contrast of light reflected and diffracted back from the regions and through a numerical aperture of the microscope. Target contrast may be achieved by controlling the diffractive properties of the regions. A grating with a pitch that causes a significant amount light to diffract out of the numerical aperture will appear darker, while a grating with a pitch that produces minimal diffraction with appear much brighter. Moreover, for a darker causing pitch, a region of layers gratings having grates stacked on each other can appear even darker, while a region having layers of grates interleaved can appear even brighter.

Wafer-based optical pattern recognition targets using regions of gratings

According to a first embodiment of the invention, a first and second reticle are used to form layers using a photolithographic process. The first and second reticles each include a grating positioned so that when the reticles are printed, the two gratings will at least partially overlap each other. The two gratings produce an interference pattern, which is used to measure overlay error.

Method and apparatus for measuring alignment of layers in photolithographic processes

Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors.

Method and apparatus for polysilicon resistor formation

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Portland, OR, United States of America

Martin Weiss