International Business Machines Corporation

Other

Martin W Sachs

Joseph C Elliott

Peter Anthony Franaszek

Marten J Halma

Paul J Brown

Kenneth R Lynch

Karl H Hoppe

Daniel Francis Casper

Gregory Michael Nordstrom

Eugene P Hefferon

Allan Samuel Meritt

Anthony S Coscarella

John H Sorg, Jr

Joseph Temple

Matthew J Kalos

Frank David Ferraiolo

Robert Edward Galbraith

Kenneth J Oakes

Leslie W Wyman

Christos J Georgiou

Daniel Manuel Dias

Asit Dan

Nagui Halim

Roger E Hough

Robert S Capowski

Linh Hue Lam

Kenneth J Fredericks

David E Stucki

Ting D Cheng

Richard Cwiakala

Frank W Brice

Robert J Gallagher

Leon Skarshinski

Fernando A Luiz

Suzanne M John

Michael C Cox

Mark C Snedaker

Gary A Fisher, Sr

Thomas M Walker

John A deVeer

John C Rathjen, Jr

Paul A Malinowski

Anujan Mangala Varma

Robert Bryan Cook

Salvatore A Calta

Thomas K Philips

Peter I Kania

Jean-Louis Fava

Edward Loizides

Caryl A Thorn

Melvin Patak

A method for automating contract negotiation between a plurality of parties over a communications network. The parties communicate and agree upon a negotiation protocol before commencing the negotiation in a meta contract that is formed to govern or control the negotiation process. The automatic negotiation may include at least one sub negotiation. Machine-executable rules are specified to enable an automatic negotiation to take place between servers over a communications network. A successful negotiation may result in the formation of an electronic commerce contract. Each party may maintain the contract state of the overall negotiation, which may take place among two or more parties, wherein at least one party may be represented by a broker. Thus, complex negotiations may be handled automatically by the inventive method. The negotiation may be conducted semi-automatically to allow for human intervention in the negotiation process.

Automated dynamic negotiation of electronic service contracts

A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is characterized as having its own memory, by either at least one channel which is independent of and coupled to the multiple physical processing nodes or by at least one input/output (I/O) processor, again which is independent of and coupled to the multiple physical processing nodes. The at least one channel and/or the at least one I/O processor couple the multiple physical processing nodes to at least one shared input/output device. Sharing of the at least one channel and/or at least one I/O processor is practical by providing 'indirect logical addressing' using logical address tables within the channel subsystem. The logical address tables associate an image identifier (Image.sub.-- ID) and processing node identifier (PN.sub.-- ID) concatenation with an indexed logical address for use in communicating I/O operation parameters across the at least one channel.

Independent channel coupled to be shared by multiple physical processing

An apparatus for illuminating the keys on keyboards includes a relatively thin transparent material having a plurality of through apertures providing clearance for each of the keys of the keyboard that are to be received therein for illuimination. The surfaces and external edges of the relatively thin transparent material is treated to prevent light from escaping therefrom, with the internal edges of the clearance through apertures being left clear for permitting the light to excape therefrom, thereby illuminating each of the keys. A bracket is adapted to removably retained a light source in the thin transparent material and permits the orientation of the light rays emanating from the light source to enter into an edge of the relatively thin transparent material. The light source is coupled to an electrical power source power and includes a fuse and an on/off switch.

Apparatus for illuminating keyboards

A computer system for using logical channel groups to indirectly address channels. The computer system includes a processor, a memory, and an input/output (IO) system for transferring information between devices and the processor. The IO system includes channels, channel path identifiers for identifying the channels, logical channel groups having lists of the channel path identifiers, and subchannels having pointers to the logical channel groups. The IO system also includes one or more switches for routing information between the channels and devices.

Indirect addressing of channels via logical channel groups

A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

Independent computer storage addressing in input/output transfers

A method and system for pipelining the processing of channel command words is provided. The channel is permitted to send commands and data to the control unit for several channel command words associated with a channel program without having to wait for responses from the control unit for prior commands sent. The channel can pipeline several commands to the control unit and the control unit can then process the commands in the order it receives them. The control unit sends responses to the channel for each command it receives acknowledging receipt of the commands.

Method and system for pipelining the processing of channel command words

A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.

Shared channel subsystem has a self timed interface using a received

A method for resolving race conditions in cascaded switches. More specifically, cross links between the cascaded switches are assigned preferred directions relative to each of the switches. A connection request or a response emanating from a switch will always use a send preference cross link if such link is available.

Resolution of race conditions in cascaded switches

A computer I/O system which includes a dynamic switch having a plurality of ports and a plurality of link-level facilities, with each link-level facility being attached to an individual one of the ports. Whenever the state of a port or its attached link-level facility is changed in such a way that the attached link-level facility's ability to communicate with another link-level facility might be affected, this fact is recognized by a dynamic switch control unit which causes a state change notification (SCN) frame to be transmitted to all other link-level facilities which might be affected. The link-level facilities receiving such a state change notification then determine if any of the associations or potential associations with the link-level facility which caused the state change notification are affected.

Notification and verification of state changes in a data processing

Provides a method for increasing the connectivity of I/O resources to a multiplicity of operating systems (OSs) running in different resource partitions of a computer electronic complex (CEC) to obtain sharing of the I/O resources among the OSs of the CEC, including channels, subchannels (devices), and control units (CUs). The invention provides image identifiers (IIDs) for assigning resources to the different OSs. Each shared I/O resource has a sharing set of control blocks (CBs) in which a respective CB is assigned to (and located by) a respective IID of one of the OSs. Each of the CBs in a sharing set provides a different image of the same I/O resource. The different CB images are independently set to different states by I/O operations for the different OSs, so that the OSs can independently share the same I/O resource.

Method and means for sharing I/O resources by a plurality of operating

Retrying a command from a CCW in a data processing I/O system having a channel connected to a control unit in which the channel detects an error condition and requests the control unit to retry the current command of an I/O operation. The control unit then determines if the requested retry can be accomplished, and, if it can, sends a response back to the channel requesting the channel to initiate a retry. After receiving the response, the channel checks to determine if conditions are still present which allow a retry, and if they are, executes the current command to perform the retry. If the control unit determines that a retry cannot be accomplished, the control unit has the option to perform a unit check procedure. If the control unit determines that neither a retry nor a unit check can be accomplished, the control unit has the option to perform a selective reset function.

Channel-initiated retry and unit check for peripheral devices

A computer system, including at least one host (processor and operating system), a channel subsystem and at least one switch (together with an associated switch controller) for switchably connecting an I/O device (together with an associated I/O device control unit) to a host via said channel subsystem, in combination with means for dynamically managing I/O connectivity in said computer from each host. The I/O manager's functions are centralized at the host level across the computer system. Each host is responsible for an instance of the manager. According to the preferred embodiment of the invention the computer system, I/O manager combination includes: (a) first means, located within each switch, for providing direct host access to the switch controller associated with a given switch; (b) second means, included in each host level instance of the manager, for automatically and dynamically determining the current I/O configuration and connectivity of each host; (c) third means, included in each host level instance of the manager, for performing System Integrated Switching (i.e., switching where any instance of the I/O manager can veto a proposed configuration change) and (d) fourth means, included in each host level instance of the manager, for insuring the integrity of the I/O connectivity database, through the use of an interlock mechanism, in a multiuser environment where each user can enter multiple part commands and processes concurrently.

Methods and apparatus for dynamically managing input/output (I/O)

In a computer I/O system including a plurality of link-level facilities and a dynamic switch having a plurality of ports, each link-level facility being attached to an individual one of the ports, a mechanism and method for assigning a unique link level address to each of the link-level facilities. As each of the link-level facilities comes on line, it sends an acquire link address (ALA) frame and waits for a response (ACK) frame. The ALA frame may be addressed to a general to-whom-it-may-concern address and have a source address of who-am-I. Only a dynamic switch normally assigns link addresses. When receiving an ALA frame, the dynamic switch returns an ACK frame having a unique link address assigned to the sender of the ALA frame. Provision is made for determining if there is a dynamic switch present, or, if the link-level facilities are connected together by a static connection through the dynamic switch, for the link-level facility of a channel to assign the unique link addresses.

Acquiring addresses in an input/output system

Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume. The use of circuit switched protocols within a token bus protocol allows more general transmission sequences and improves the utilization of token bus bandwidth.

Dynamic switch protocols on a shared medium network

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Westport, CT, United States of America

Martin W Sachs