Infineon Technologies Ag

Qimonda Ag

Infineon Technologies North America Corp.

Technische Hochschule Rosenheim

Martin Versen

Klaus Nierle

Peter Beer

Erwin Thalmann

Frank Adler

Manfred Moser

Helmut Schneider

Oliver Kiehl

Martin Perner

Heinz Langhals

Jörg Kliewer

Michael A Killian

Peter Thwaite

Joerg Kliewer

Thomas Huber

Ernst Stahl

Achim Schramm

Grant McNeil

Changduk Kim

Thomas Neyer

Lee Nino

Daewon Lee

Zach Johnson

Maximilian Wohlschläger

Method and system for testing an integrated circuit

A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

Sense-amplifier circuit for a memory device with an open bit line architecture

The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

Test method for determining the wire configuration for circuit carriers with components arranged thereon

A method and apparatus for reducing power consumption of a memory device. The method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective word lines to the precharge voltage.

Redundant wordline deactivation scheme

Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Method and apparatus for checking output signals of an integrated circuit

The invention provides a device for monitoring electronic circuit units during an initialization phase. The device has at least one internal data line () for forwarding internal data () in the electronic circuit unit () and at least one data connection line () for outputting the internal data from the electronic circuit unit () and for inputting external data () into the electronic circuit unit (). A changeover unit (), which is intended to change over the data connection line () either to the internal data line () or to internal signal lines (), and a combinational logic unit () for combining an initialization signal (), which is provided by the electronic circuit unit () to be monitored, with an external changeover signal (), which is supplied via a changeover signal input () of the electronic circuit unit () to be monitored, are also provided. An activation signal (), which is output by the changeover unit (), is used to change over the data connection line to the internal signal lines () when the initialization signal () indicates an initialization mode of the electronic circuit unit ().

Monitoring device for monitoring internal signals during initialization of an electronic circuit

A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.

Test mode method and apparatus for internal memory timing signals

A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals. The module is electrically coupled to the processor. The at least one manufactured semiconductor device is mounted on the module, and the semiconductor device has a plurality of pins at least one of which is a non-functional pin. The system is configured to provide the processor access to the semiconductor device. An external device monitors voltage at the non-functional pin of the semiconductor device.

Voltage monitoring test mode and test adapter

Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Serial presence detect functionality on memory component

A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Test mode for IPP current measurement for wordline defect detection

An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

Integrated semiconductor memory with redundant memory cells

In a method for testing an electric circuit, a first circuit is produced by a first process sequence. A first signal is applied to the first circuit and a signal indicating if the first circuit is defective is generated by comparing the first signal with the first circuit output signal. Then, a second circuit is produced by a second process sequence which includes incorporating at least one intentional defect structure. The first signal is applied to the second circuit and a signal is generated by comparing the first signal with the second circuit output in response to the first signal. A modified signal is applied to the second circuit, until a comparison of the modified signal and the respective response of the second circuit indicates a defective second circuit. Information about the modified signal resulting in the indication of a defective second circuit is stored.

Method for testing an electric circuit

A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an adjacent word line. The memory cells along the first word line and bit lines, respectively, connected to them are subsequently connected simultaneously to a common data line via sense amplifiers, respectively, connected to them. The sense amplifiers assess the memory cells burdened by the disturbance signal and the capacitive load of the common data line and, respectively, refresh the disturbed memory state in the memory cells. The memory state refreshed in the memory cells is subsequently assessed in the context of a fast read access.

Method for testing an integrated semiconductor memory

A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.

Method for the defect analysis of memory modules

DRAM memory device () comprising at least one array of memory cells (), each memory cell () being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (); a controllable active-current generator () for providing power to the sense amplifiers and pre-charge circuits () for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device () and an assigned switching time; a controllable standby-current generator () for providing power to the sense amplifiers and pre-charge circuits () after the switching time; a control circuit () for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator () and the standby-current generator (); wherein the control circuit () is adapted to control the time for switching the respective power generator () to the sense amplifiers and to the pre-charge circuits () subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits ().

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Feldkirchen-Westerham, Germany

Martin Versen