Infineon Technologies Ag

Martin Verhoeven

Nicolas Nagel

Dirk Manger

Matthias Markert

Dirk Caspary

Thomas Zell

Hocine Boubekeur

Thomas Tatry

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiOand SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Hard mask layer stack and a method of patterning

The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

Charge-trapping memory cell and charge-trapping memory device

The hydrodynamic effects&#x2014;which occur during immersion lithography as a result of the movement of the semiconductor wafer&#x2014;in a liquid preferably provided between the last lens surface of the projection system and the semiconductor wafer can be avoided by means of a movable illumination region for illuminating a cutout of a mask containing a structure to that can be imaged onto the semiconductor wafer. A scan movement of the mask and the semiconductor wafer can be either reduced or entirely avoided by means of a movement of the illumination region.

Method and imaging apparatus for imaging a structure onto a semiconductor wafer by means of immersion lithography

In a charge trapping memory cell, programming occurs by trapping hot electrons from the channel region in a storage layer. The erasure occurs by Fowler-Nordheim tunneling of the electrons through the lower boundary layer to source or drain or preferably through the upper boundary layer into the gate electrode. The boundary layers are preferably aluminum oxide.

Charge trapping memory cell

Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.

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Radebeul, Germany

Martin Verhoeven