Atmel Corporation

Maxim Integrated Products, Inc.

Actel Corporation, Inc.

Aim Controls, Inc.

Martin T Mason

Frederick Furtek

Robert B Luking

Patrick Yin Chan

Arman Hematy

Pierre Haubursin

Ajithkumar Venkata Dasari

David Andrew McConnell

Arkadii V Samoilov

Theodore M Speers

Peter R Harper

Patrick H Dwyer

Scott Carlton Evans

Harry H Kuo

Leland M Farrer

Nancy D Kunnari

Jamaal Mitchell

Sandeep S Aranake

A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.

Enhanced board level reliability for wafer level packages

Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port. These capabilities can be combined with its multi-range, high voltage and high current capability to increase functionality.

Programmable mixed-signal input/output (IO)

An example programmable multichannel data converter includes a multiplexer having a plurality of input channels, an output and a channel selector input, a converter having an input coupled to the output of the multiplexer, and a controller having a user-configurable memory stack and control circuitry, the controller having a channel selector output coupled to the multiplexer.

Programmable multichannel signal selector

An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

Field programmable gate array including a non-volatile user memory and method for programming

Method for implementing a physical design for a dynamically reconfigurable logic circuit

A programmable logic chip and configuration memory chip are mounted within a multi-chip module to form a single package. The configuration memory has a security bit which in a first state allows programming and read-back of configuration data in the memory chip via external pins of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.

Secure programmable logic device

A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of reset lines which include main reset lines, column reset lines, and sector reset lines. Each of the main reset lines receives a different reset signal. Each of the column reset lines is associated with a particular column of logic cells of the matrix. Each column reset line is selectively connectable to any one of the main reset lines to receive a selected reset signal. Each of the sector reset lines is connected to a subset of the logic cells in a column. The column reset lines are selective connectable to the logic cells in this respective associated columns by means of the sector reset lines that are connectable to the column reset lines.

FPGA structure having main, column and sector reset lines

A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

Software tool to allow field programmable system level devices

A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of clock lines which include main clock lines, column clock lines, and sector clock lines. Each of the main clock lines receives a different clock signal. Each of the column clock lines is associated with a particular column of logic cells of the matrix. Each column clock line is selectively connectable to any one of the main clock lines to receive a selected clock signal. Each of the sector clock lines is connected to a subset of the logic cells in a column. The column clock lines are selective connectable to the logic cells in this respective associated columns by means of the sector clock lines that are connectable to the column clock lines. A circuit for selectively inverting clock signals may be located along each sector clock line.

FPGA structure having main, column and sector clock lines

A field programmable gate array has a matrix of programmable logic cells and a bus network of local and express bus lines. The bus network effectively partitions the matrix into blocks of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders between blocks creates spaces at the corners of blocks that can be filled with RAM blocks, other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks can be single or dual port SRAM addressed through the bus lines. Pairs of adjacent columns of RAM blocks may be commonly addressed by the same set of bus lines. Other specialized or dedicated logic might also fill those corner spaces. Logic cells are directly connected to neighboring cells, including diagonally adjacent cells, and are also connected to local bus lines. The arrangement of express bus lines is preferably staggered in such a way that they connect to non-consecutive repeaters in an alternating manner. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.

FPGA logic cell internal structure including pair of look-up tables

A field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed. Logic cells are directly connected to neighboring nearest cells, including diagonally and orthogonally adjacent cells, and are also connected to local bus lines. Such direct cell-to-cell connections allow both directions of signal propagation. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, I/O pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.

Field programmable gate array having access to orthogonal and diagonal

An H-Bridge motor controller having a floating, electrically isolated high side FET driver design where the motor driver circuity is electrically isolated from the logic circuitry. Back EMF generation during motor operation is minimized by employing a 'fifth' power transistor to the H-Bridge that connects the motor coil to ground when the other transistors in the H-Bridge are turned off, so as to provide a direct path for the unused energy to be removed from the driver circuit without interfering with the normal switching of the FETs. Alternatively, back EMF generation is minimized by applying switching signals to the H-Bridge where, instead of turning the low side FET drivers between motor clocks, the low side FET drivers are both turned on during the 'off time' period, so as to connect both ends of the motor coil to ground during the 'off' period, thereby draining the coil of unused energy. The fifth power transistor also permits either one-half or the entire motor coil to be connected to the H-Bridge at the commencement of the energizing phase, thereby altering the inductive load seen by the H-Bridge upon motor energization. The motor controller also includes analog and digital circuits that automatically vary the voltage and/or current applied to the motor depending upon performance characteristics such as speed, electromagnetic characteristics and torque load.

Motor control apparatus

A system and method for partial reconfiguration of a gate array includes generating a netlist by placement and routing of a logic circuit. The netlist is accessed to modify logic cells configurations created by the place and route operation. Based on the modifications, a partial configuration bitstream containing only bitstrings which implement the modified logic cells is created. The partial configuration bitstream is downloaded to the gate array, thereby effectuating a partial reconfiguration of the gate array. In an alternate embodiment, a system in accordance with the present invention includes software utilities which allow an application program executing in a system containing a programmable gate array to reconfigure the array on-the-fly. The utilities include routines for modifying the design in response to external conditions detected during run-time. This approach obviates the need for providing a set of predetermined alternate designs, allowing the application to make that determination on its own.

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San Jose, CA, United States of America

Martin T Mason