Intel Corporation

Raytheon Company

Other

Tektronic, Inc.

Martin Spence Denham

Rachael Jade Parker

Daniel G Knierim

Keng L Wong

Darin Scot Williams

Christian M Boemler

Jeffrey E Smith

Kaizad Rumy Mistry

Wenliang Chen

Mohsen Alavi

David U Fluckiger

Eric J Beuville

Robert C Gibbons

Roshan J Fernando

Patrick John Ott

Paul Gregory Slankard

Bruce E Bozovich

A Secure Hash Algorithm 256 (SHA-256) expander operates over multiple cycles to convert 16 message words, M(t), into 64 working values, W(t), for input into a SHA-256 compressor. As the expander operates to produce W(t), it computes partial values of W(t) as soon as the necessary data operands are available in cycle time. Once computed, the partial values are retained and shifted and any unneeded original shift source values are discarded. When the shift register outputs finally arrive at the output, W(t) is already computed. The expander allows for one-write-port, one-read-port register files to be used in some integrated circuit embodiments. The expander also leads to improvements in adder delays, energy consumption, and area consumption when implemented as an integrated circuit.

Secure hash algorithm implementation

According to one aspect, a Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) is provided. The ROIC includes an input to couple to a photodetector array including a plurality of photodetectors and is configured to generate compressed image data by sampling and summing the values of the plurality of photodetectors consistent with a set of Compressive Sampling Measurement Matrices and provide the resulting coded aggregates to a signal processor as compressed image data.

Read-out integrated circuit with integrated compressive sensing

According to one aspect, embodiments herein provide a current to frequency converter comprising a node configured to be coupled to a photodetector and to receive a photo-current from the photodetector, a capacitor having a first terminal and a second terminal and configured to accumulate electrical charge derived from the photo-current on the first terminal and the second terminal, a switch network configured to selectively couple one of the first terminal and the second terminal to the node, and a Master-Slave (MS) Flip Flop (FF) coupled to the switch network and configured to operate the switch network to toggle which of the first terminal and the second terminal is coupled to the node based on a voltage at the node.

Current to frequency converter

Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a crossbar and a number of interconnect branches coupled to the crossbar. Each of the interconnect branches includes a number of connector circuits coupled in series to transfer data in a group of devices of the plurality of devices. The crossbar includes a number of connector circuits coupled in series to allow one group of devices from one interconnect branch to exchange data with another group of devices from another interconnect branch. Other embodiments are described and claimed.

Modular interconnect structure

The accumulation of registered sub-frame residuals in an address-mapped repartitioned digital pixel matches the intensity resolution (dynamic range) to the spatial resolution of the image. The digital accumulation of pixel quantization events (QEs) is extended to include sub-frame residuals. After all QEs are digitally accumulated, then removed from the analog accumulator, an analog residual value remains. Residual capture logic is configured to trigger residual digitization logic at least twice per frame interval for selected pixels to capture, digitize and then clear the residual value on the storage device. Memory update logic is configured to accumulate the quantization event digital values and residual digital values into existing digital values at the address-mapped memory locations in digital memory. Resolution enhancement is enabled by an address mapping that maps a one-pixel spacing on the detector to two or more pixel spacing in the digital memory.

Address mapped repartitioned digital pixel with sub-frame residual accumulation

Systems and methods for configuring an infrared thermal imaging system using a video interface of an electronic device, such as a microcontroller, for example, for sending commands and control information. In one example a an infrared thermal imaging system includes a focal plane array (FPA) of infrared detectors, the FPA being configured to generate an output signal in response to infrared radiation impinging thereupon, read out integrated circuitry (ROIC) operatively coupled to the FPA, and a microcontroller having at least one video display interface operatively coupled to the ROIC, the microcontroller being configured to send data to the ROIC via the at least one video display interface, the data including command data.

Infrared thermal imaging system and method

An imaging system includes an array of pixel cells and a plurality of digital memory elements disposed physically separate from and coupled to the array of pixel cells. Each of the pixel cells includes a photodetector, an electrical storage device coupled to the photodetector, and quantization circuitry coupled to the electrical storage device. The photodetector is configured to generate a photo-current in response to light impinging thereon. The electrical storage device is configured to accumulate an electrical charge from the photo-current. The quantization circuitry is configured to convert the electrical charge into an analog quantization event signal. Each of the digital memory elements is in electrical communication with at least one of the pixel cells and is configured to store a digital value in response to receiving the analog quantization event signal from the at least one of the pixel cells.

Repartitioned digital pixel

According to one embodiment, a method includes generating a first clock signal and a second clock signal with non-overlapping clock phases. The method may further include latching, by a plurality of master latches of a shift register, a plurality of values at a plurality of inputs of the master latches in response to a particular type of logical transition of the first clock signal. The method also includes latching, by a plurality of slave latches of the shift register, a plurality of output values of the plurality of master latches at a plurality of inputs of the slave latches in response to a particular type of logical transition of the second clock signal.

Shift register with two-phase non-overlapping clocks

Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2unique addresses from unique combinations of the plurality of first-stage decoded address outputs.

Apparatus and method for decoding an address in two stages

According to one embodiment of the present disclosure, a focal plane array is provided. The focal plane array may comprise a plurality of pixels. Each pixel may include one or more capacitors operable to collect charge corresponding to an amount of light received at the respective pixel. Each pixel may further include a present state register operable to store a present state value of the respective pixel. The present state value indicates an amount of charge collected by the one or more capacitors of the respective pixel. The focal plane array may further include a logic circuit coupled to each present state register of the plurality of pixels. The logic circuit is operable to compute a next state value of each pixel based on the present state value of the respective pixel. The logic circuit may be time shared by the pixels.

Compact digital pixel for a focal plane array

A method and apparatus for repairing digital addressable structured arrays, such as memory devices. In one example, a repair mechanism includes adding a number of redundant repair elements to the array, and coupling one or more skip units to the array ahead of the address decode unit(s). The skip unit compares a received logical address with a skip address identifying a defective element within the array, and modifies the input address based on a comparison of the input address and the skip address. The modified address is then decoded to access an element of the array.

Repair device and method for integrated circuit structured arrays

A precision charge dump circuit configured to transfer preset quanta of charge to or from a first capacitor (for example, an integration capacitor in an in-pixel ADC circuit). In one example, the charge dump circuit uses a second capacitor that is pre-charged with the preset quanta of charge to determine the preset value of the quanta of charge, and an amplifier in a voltage-follower mode to cause the charge subtraction or addition.

Precision charge-dump circuit

A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Method and apparatus for serializing bits

Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.

Growing community of inventors

Bend, OR, United States of America

Martin Spence Denham