Sun Microsystems, Inc.

Fujitsu Corporation

Martin Sodos

Toshio Ogawa

Takeshi Shimizu

Patrick N Conway

Kazunori Masuyama

Sudheer Miryala

Jeremy J Farrell

Thomas Chan

A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.

Method and system for logical partitioning of cache memory structures in a partitoned computer system

A method and apparatus for supporting multiple DMA channels by splitting data transfers for each channel into sequences of data slices and interleaving on a slice-by-slice basis. While the control of transfer resources may be shifted among the DMA channels, the ordering of the data slices for each channel is preserved. The present invention also discloses a circuit architecture capable of supporting the multiple interleaving DMA channels. The circuit architecture comprises a dual-port memory, channel sequencer, and channel interleave control. The dual-port memory stores slices of data to be transferred through the channels. A channel sequencer maintains the channel ordering of data slices in the dual-port memory. A channel interleave control unit allows channels to interleave their data transfers by monitoring the channel interleave size, current data transfer count and total transfer count per channel. A second channel is allowed to transfer data through the same medium as a first channel either when the first channel has reached its channel interleave size, or when the first channel has transferred its requested total transfer count, thus providing efficient bus utilization.

Method of and apparatus for interleaving multiple-channel DMA operations

Method and apparatus for transferring data between a memory and a

An apparatus and method for performing direct memory access (DMA) to input/output (I/O) devices are described. In order to overcome storage limitations of a DMA controller, channel control blocks (CCBs) are stored in external memory. The DMA controller is programmed to reference a particular address of the external memory when a predetermined bit, referred to as a chain bit, in a current channel control block is set. The DMA controller will then perform a memory read operation on that area of memory and store a retrieved channel control block at a location previously utilized by an earlier channel control block. This process will continue until the chain bit is reset, at which time a DMA operation is complete. Dynamic chaining is easily accommodated whereby channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. The apparatus and method may be used to implement dynamic chaining without incurring race conditions. A wait bit is provided in each channel control block and, when this bit is set, the DMA controller will suspend operations thereby providing an opportunity for updating a chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.

Method and apparatus for dynamic chaining of DMA operations without

An improved computer system bus is disclosed that transitions between addressed data transfers and handshake data transfers on the fly and that performs burst within dynamic data sizing during a data transfer sequence without prematurely terminating the sequence and that changes between synchronous and asynchronous data transfer sequences on the fly. These capabilities are accomplished by modifying the function of bus signal lines depending upon the type of transfer sequence undertaken. On the fly transition between addressed data transfer and handshake data transfer is accomplished by providing a set of DMA acknowledge signals and modifying their function according to the type of data transfer sequence underway. Burst within dynamic data sizing during a sequence is performed by taking advantage of burst transfer capabilities of the slave device, and the capability of the master device to modify data width on the fly. If the slave supports burst transfer, the bus master proceeds with a burst transfer sequence for the remaining portions of the data while shifting the data to accommodate the data width limitation of the slave device. On the fly transition between a synchronous transfer sequence and an asynchronous transfer sequence is accomplished by modifying the timing of bus acknowledge signals.

Versatile peripheral bus

In the system of the present invention, the limitations imposed by the physical limitations of the DMA controller are overcome by storing the channel control blocks in external memory. The DMA controller is programmed to reference a particular address of external memory when a predetermined bit in the current channel control block is set. The DMA controller will then perform a memory read operation on the area of memory referred to by that address in order to store the retrieved channel control block at a location previously utilized by a earlier channel control block. This reading process will continue until the bit is reset, at which time the DMA operation is complete. Dynamic chaining is accommodated whereby the channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. Furthermore, a method and apparatus for implementing dynamic chaining without incurring race conditions is described. A wait bit in each channel control block is provided when this bit is set, the DMA controller will suspend operations thereby providing opportunity for updating the chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.

Method and apparatus for the prevention of race conditions during

A method and apparatus for arbitrating among multiple requested data transfers based on the availability of transfer resources. A request for the control of a resource is transmitted to an arbiter with information regarding the size of data transfer, internal buses and external buses required. The arbiter compares the information with the space remaining in the buffer, internal bus availability and external bus availability. If all the resources are available to complete the request, then the request is granted arbitration and the requested transfer is started. If any of the resources is not available, the arbiter takes the next request for evaluation. A mechanism is also provided for each request to require the arbiter to wait until all the resources are available to prevent the arbiter from taking on the next request.

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San Jose, CA, United States of America

Martin Sodos