U.S. Philips Corporation

Thomson Licensing S.a.

Martin Seitz

Rolf Ernst

Sieghard Hasenzahl

Peter R&uuml;ffer

Lutz Buettner

Elmar Maas

In an arrangement for processing digital video data there is provided for the most universal use of the arrangement and for a fast data exchange between components inside the arrangement. The arrangement utilizes at least one video data computer, at least one video data interface and at least one standard computer and/or one video hardware component, between which the video data can be exchanged through a fiber channel. The video data computer and the video interface(s) are controlled by at least one control computer via an Ethernet bus.

Arrangement for processing video data

A circuit arrangement for automatically recognizing the line number of a video sync signal in accordance with the 525 or 625 line standard, this circuit arrangement automatically generating a control signal corresponding to one of the relevant line numbers. To recognize the line number, a line counter (14) clocked with horizontal frequency pulses is provided, this line counter receiving the frame-frequency sync pulse signal as a reset signal. Moreover, a decoding stage (15) is arranged at the output of the line counter (14), which supplies a signal for changing the line standard hitherto used and a signal characterizing the corresponding line standard. In a subsequent signal evaluation circuit (16), these two signals are checked and a control signal either corresponding to the current line standard or to the new line standard is applied to the output (17).

Circuit arrangement for automatically recognizing the line standard of a

A circuit arrangement for deriving horizontal frequency and vertical frequency pulses from a synchronizing signal, in which all clocked components are provided with the same clock during the digital processing of the synchronizing signal. Too derive the horizontal (H) pulse signal, a logic circuit 2 is provided which combines the sync signal with a masking pulse signal derived from the clocked sync signal. To derive the vertical (V) pulse signal in the clock raster, a counting flip-flop 14 is driven by the clocked sync signal after combination with the vertical pulse signal via an interference pulse signal suppression circuit 10. To derive the 2V pulse signal, a logic circuit 17 is provided which combines the V pulse signal with a pulse signal derived from the clocked sync signal.

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Ober-Ramstadt, Germany

Martin Seitz