International Business Machines Corporation

Martin Schwidefsky

Wolfgang Gellerich

Lisa Cranton Heller

Chung-Lung K Shum

Peter M Held

Damian Leo Osisek

Hubertus Franke

Reinhard Theodor Buendgen

William Alan Holder

Randall W Philley

Ingo Adlung

Ray Mansell

Jong Hyuk Choi

Jonathan D Bradbury

Gustav E Sittmann, Iii

Christian Borntraeger

Gerrit Koch

Kai Oliver Weber

Heiko Carstens

Philippe Bergheaud

Christian Jacobi

Fadi Y Busaba

Angel Nunez Mencias

Christoph Raisch

Jakob Christopher Lang

Ulrich Weigand

Louis P Gomes

Carsten Otte

Peter Altevogt

Albert Schirmer

Martin Bernhard Schmidt

Jochen Schweflinghaus

Viktor Mihajlovski

Gustav E Sittman, Iii

Michael Holzheu

Holger Smolinski

Christian Ehrhardt

Randall Philley

Jong Hyuk Ibm Uk Limited Choi

Gustav Sittmann 111

An initial program load of a system component of a computing environment is performed. A determination is made as to whether one or more signatures of one or more signed binary code components relating to the system component are verified. Based on determining that the one or more signatures are verified, additional verification is performed. The additional verification includes obtaining a select binary code component of one or more binary code components relating to the system component and determining whether the select binary code component is a particular signed binary code component. Based on determining that the select binary code component is the particular signed binary code component, a check is performed. The initial program load is continued based on a successful check.

Secure initial program load

An example computer-implemented method includes presenting, by a hardware control of a computing system, an exception to an untrusted entity when the untrusted entity accesses a secure page stored in a memory of the computing system, the exception preventing the untrusted entity from accessing the secure page. The method further includes, in response to the exception, issuing, by the untrusted entity, an export call routine. The method further includes executing, by a secure interface control of the computing system, the export call routine.

Program interruptions for page importing/exporting

A method is provided. The method is implemented by a secure interface control of a computer that prevents unauthorized accesses to locations in a memory of the computer. The secure interface control determines that a host absolute page is not previously mapped to a virtual page in accordance with securing the host absolute page and a host virtual page is not already mapped to an absolute page in accordance with securing the host absolute page.

Secure interface control high-level page management

According to one or more embodiments of the present invention, a computer implemented method includes computing a hash value of a page of memory of a computer system and comparing the hash value with a previously computed hash value of the page. A per-encryption value per page can be used in encrypting the page based on determining that the hash value matches the previously computed hash value. A modified value of the per-encryption value per page can be used in encrypting the page based on determining that the hash value mismatches the previously computed hash value.

Secure paging with page change detection

A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task and storing the task-relating branch prediction data of the second task in the branch prediction history table.

Method for maintaining a branch prediction history table

Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.

Branch prediction for indirect branch instructions

A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Load register on condition immediate instruction

The present disclosure relates to storing data in a computer system. The computer system comprising a main memory coupled to a processor and a cache hierarchy. The main memory comprises a predefined bit pattern replacing existing data of the main memory. Aspects include storing the predefined bit pattern into a reference storage of the computer system. At least one bit in a cache directory entry of a first cache line of the cache hierarchy can be set. Upon receiving a request to read the content of the first cache line, the request can be redirected to the predefined bit pattern in the reference storage based on the value of the set bit of the first cache line.

Storing data into a memory

A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.

Data prefetching that stores memory addresses in a first table and responsive to the occurrence of loads corresponding to the memory addresses stores the memory addresses in a second table

Processing within a computing environment that supports pageable guests is facilitated. Processing is facilitated in many ways, including, but not limited to, associating guest and host state information with guest blocks of storage; maintaining the state information in control blocks in host memory; enabling the changing of states; and using the state information in management decisions. In one particular example, the guest state includes an indication of usefulness and importance of memory contents to the guest, and the host state reflects the ease of access to memory contents. The host and guest state information is used in managing memory of the host and/or guests.

Facilitating processing within computing environments supporting pageable guests

Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.

Quality of cache management in a computer

A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.

Selective purging of entries of structures associated with address translation. A request to purge entries of a structure associated with address translation is obtained. Based on obtaining the request, a determination is made as to whether selective purging of the structure associated with address translation is to be performed. Based on determining that selective purging is to be performed, one or more entries of the structure associated with address translation are purged. The selectively purging includes clearing the one or more entries of the structure associated with address translation for a host of the computing environment and leaving one or more entries of one or more guest operating systems in the structure associated with address translation. The one or more guest operating systems are managed by the host.

Selective purging of entries of structures associated with address translation in a virtualized environment

Load register on condition immediate or immediate instruction

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Boeblingen, Germany

Martin Schwidefsky