Qualcomm Incorporated

Intel Corporation

Martin Saint-Laurent

Paul Bassett

Baker Mohammad

Prayag Bhanubhai Patel

Sanjay Bhagawan Patil

Daniel Lawrence Stasiak

Lam Ho

Carlos Andres Rodriguez Ancer

Bhavin Shah

Sei Seung Yoon

Chulmin Jung

Animesh Datta

Rui Li

Bin Liang

Lucian Codrescu

Suresh Kumar Venkumahanti

Eric W Mahurin

Mohamed Hassan Abu-Rahma

Christopher E Koob

Alan G Lewis

Yan Zhang

Nam Dang

Marzio Pedrali-Noy

Ramaprasath Vilangudipitchai

Esin Terzioglu

Rajit Chandra

Xuhao Huang

Seid Hadi Rasouli

Pratyush Kamal

Boris Andreev

Xufeng Chen

Jentsung Lin

Manojkumar Pyla

Ali Akbar Merrikh

Mohamed Waleed Allam

Rajeev Jain

Paras Gupta

Jay Madhukar Shah

Joseph Victor Zanotelli

Kashyap Ramachandra Bellur

Swarna Navubothu

Mohammad Ghasemazar

Peeyush Kumar Parkar

Sachin Bapat

Yuhe Wang

HariKrishna Chintarlapalli Reddy

Jen Tsung Lin

Varun Verma

Tung Nang Pham

Joseph Terregrossa

Somasekhar Maradani

Bassam Jamil Mohd

Haytham Samarchi

Harikrishna Chintarlapalli Reddy

Christopher Edward Koob

Paul D Bassett

Baker S Mohammad

Jamil Bassam Mohd

Ken Tsung Lin

Prayag Patel

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Apparatus and methods for reducing clock-ungating induced voltage droop

Aspects of the disclosure are directed to voltage-based current sensing. In accordance with one aspect, voltage-based current sensing may include performing a coarse calibration of a voltage based current sensor to determine a coarse offset; performing a fine calibration of the voltage based current sensor to determine a fine offset; performing a frequency calibration of the voltage based current sensor to determine a frequency offset; and performing a transfer function calibration of the voltage based current sensor to determine a sensor transfer function using one or more of the coarse offset, the fine offset and the frequency offset; and measuring a load current using the sensor transfer function.

Differential current sensing with robust path, voltage offset removal and process, voltage, temperature (PVT) tolerance

A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

Temporal temperature sensor position offset error correction

Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.

Controlling voltage deviations in processing systems

A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

Voltage droop control

Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.

Supply voltage node coupling using a switch

A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

System and method for reducing cross coupling effects

A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Flip-flop with reduced retention voltage

A method includes receiving, at a voltage regulator, an activity adjustment signal from a digital circuit. The method also includes controlling one or more variable impedance elements of the voltage regulator to modify an output voltage provided to the digital circuit. The output voltage is based at least in part on the activity adjustment signal.

Voltage regulator with variable impedance element

A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.

Multiple critical paths having different threshold voltages in a single processor core

A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Length-of-diffusion protected circuit and method of design

According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Data storage for voltage domain crossings

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Austin, TX, United States of America

Martin Saint-Laurent