Lsi Corporation

Agere Systems Inc.

Martin S Dell

Michael Scott Hicken

Matthew Tota

Timothy W Swatosh

Wei Li

Jackson L Ellis

Yung-Terng Wang

Zbigniew M Dziong

Pamela Hempstead

Vinay Ashok Somanache

Yu-Kuen Ouyang

John Leshchuk

Walter A Roper

Pamela S Hempstead

A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.

Meta data handling within a flash media controller

A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.

Flexible flash commands

A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2data locations and K spare locations. At least one page in the memory has 2user data sectors and each sector has 2+L locations therein. Because L is at least 1 but less than 2, user data is stored in the spare memory locations. By storing user data in spare locations that were previously off-limits to user data, enterprise-sized sectors can be efficiently stored in flash memories with little wasted memory, thereby making flash-memory systems compatible with existing hard-drive storage systems in enterprise system applications.

Flash memory organization

A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2data locations and K spare locations. At least one page in the memory has 2&#x2212;1 user data sectors and each sector has 2+L locations therein. Error-correction code (ECC) data related to the user data is calculated and stored in at least the 2user data locations unused by the 2&#x2212;1 user data sectors. Because L is at least 1 but less than 2(N&#x3e;M), at least a portion of one user data sector is stored in the spare memory locations. Additional locations in each page are available to allow for the ECC data to have additional redundancy bits added per sector, thereby making the flash memory system more robust and reliable.

A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. In one aspect, at least one input port can be programmably configured to store data in two or more input routing queues that are associated with a single output port, and at least one output port can be programmably configured to receive data from two or more output routing queues that are associated with a single input port. In another aspect, the output stage transmits status information about the output stage to the input stage, which uses the status information to generate bids to request connections through the switching stage. In yet another aspect, the switching stage transmits a grant/rejection signal to the input stage identifying (1) whether each bid is accepted or rejected and, if rejected, (2) a reason for rejecting the bid, and the input stage determines how to react to a rejected bid based on the reason the bid was rejected.

Three-stage switch fabric with input device features

In one embodiment, queues associated with a first traffic class (FTC) are selected for service. Each FTC queue having at least one enqueued cell is identified as an occupied FTC queue, Where at least one FTC queue is provisioned for burst scheduling of multiple cells when serviced. An occupied FTC queue provisioned for burst scheduling is identified as a super-occupied FTC queue when the number of cells enqueued is greater than a specified number. Each occupied FTC queue is set as eligible for service based on a FTC scheduling algorithm. An eligible FTC queue is selected for service based on a corresponding sub-priority of each eligible FTC queue. Each FTC queue is assigned a sub-priority based on a service level of a connection associated with enqueued cells. When the super-occupied queue is serviced, the number of cells dequeued is based on a burst size.

Scheduler for a packet routing and switching system

A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. Each input device of the input stage transmits bids to the crossbar devices of the switching stage to request connections through the switching stage for routing the data to the output devices of the output stage. In one aspect, each crossbar device has (1) a bid arbitrator that determines whether to accept or reject each received bid, wherein, in response to a collision between multiple bids, the bid arbitrator accepts two or more of the colliding bids in a single time slot; and (2) memory for storing one or more accepted cells for the same output device, wherein the crossbar device can transmit grant signals for two or more accepted bids for the same output device in a single time slot. In another aspect, the bid arbitrator is configured to re-consider whether to accept a stored bid that was not accepted in a previous time slot.

Three-stage switch fabric with buffered crossbar devices

Integrated circuits are disclosed which implement multiple channel media access control devices for controlling network communications. The integrated circuits include multiple channel slices which output data for transmission through the network. Each of the channel data are input to a single data memory, which reduces the size of the integrated circuit. Since only one data memory is used to buffer data from multiple channels, the data are first retimed from individual media access control circuit clock domains to a common host clock domain and then scheduled for output to the host. By retiming the data, integrated circuit signal throughput is enhanced. Deeply embedded transmit and receive FIFOs are provided to receive the channel data and implement shared memory access.

System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain

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Bethlehem, PA, United States of America

Martin S Dell