International Business Machines Corporation

Globalfoundries Inc.

Martin Recktenwald

Christian Jacobi

Aaron Tsai

Christian Zoellin

Anthony Saporito

Hans-Werner Tast

Christian Habermann

Willm Hinrichs

Aditya Nitin Puranik

Ulrich Mayer

Chung-Lung K Shum

Timothy John Slegel

Eyal Naor

Jonathan D Bradbury

Markus Kaltenbach

Markus Helms

Gerrit Koch

Donald W Schmidt

Mark S Farrell

Bruce C Giamei

Uwe Brandt

Ralf Winkelmann

Johannes C Reichart

Walter Heinrich Lipponer

Brian Robert Prasky

Jane Helen Bartik

Patrick M West, Jr

Alper Buyuktosunoglu

Angel Nunez Mencias

Cedric Lichtenau

Jakob Christopher Lang

Khary J Alexander

Thomas Pflueger

Jonathan T Hsieh

Yossi Shapira

Rolf Bernhard Hilgendorf

Dwifuzi Coe

Charles Franklin Webb

James J Bonanno

Vijayalakshmi Srinivasan

Brian William Curran

Frank Siegfried Lehnert

Scott Barnett Swaney

Girish Gopala Kurup

John-David Wellman

Barry Watson Krumm

Thomas G Koehler

Timothy J Siegel

Deanna P D Berger

Jens Kuenzer

Joshua M Weinberg

Yair Fried

Simon H Friedmann

Andreas Schmid

Michael F Fee

Ute Gaertner

Peter Anthony Sandon

Tobias Webel

Michael J Cadigan, Jr

Sascha Junghans

Preetham M Lobo

Christian Borntraeger

Michael Billeci

Diana Lynn Orf

Ramon Bertran Monfort

Erez Barak

Eberhard Engler

Srinivas Bangalore Purushotham

Deepankar Bhattacharjee

Pradeep Bhadravati Parashurama

Gregory Miaskovsky

Christian Gerhard Zoellin

Nidhi Chandak

Khary J ALexander

Bruce Conrad Giamei

Donald William Schmidt

Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Controlling storage accesses for merge operations

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Translation support for a virtual cache

A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Reducing cache transfer overhead in a system

Aspects include circuitry that includes a first global generation counter (GGC) that is increased upon decoding of a branch instruction and a second GGC that is increased upon a completion of the branch instruction. Upon a triggered rollback, the first GGC is reset. The circuitry also includes a generation tag memory associated with a register that receives loads during a side-channel attacks which is set to the first GGC upon a first load, and a determination unit to determine, for a second load from an address depending on the register of the first load, a generation tag value associated with the register of the second load as a function of the first GGC, the second GGC, and the generation tag value associated with the register of the first load. A wait queue is configured to block the second load, if the generation tag is larger than the second GGC.

Hardware mitigation for Spectre and meltdown-like attacks

Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.

Voltage droop management through microarchitectural stall events

Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Cache structure using a logical directory

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Saving and restoring machine state between multiple executions of an instruction

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Sort and merge instruction for a general-purpose processor

Technology for decrypting and using a security module in a processor cache in a secure mode such that dynamic address translation prevents access to portions of the volatile memory outside of a secret store in a volatile memory.

Computer system software/firmware and a processor unit with a security module

Methods testing a data coherency algorithm via a simulated multi-processor environment are provided, which include implementing: (i) a transactional footprint keeping the address of each cache line used by the processor core, (ii) a reference model operating on and keeping a set of timestamps for a cache line, the set including a construction date representing a global timestamp when new data arrives at a private cache hierarchy and an expiration date representing another global timestamp when a cross-invalidation hits the private cache hierarchy, (iii) a core observed timestamp representing a global timestamp of an oldest construction date of data used before, and (iv) interface events monitoring instruction sequences guaranteed by transactional execution to ensure atomicity of a transaction. Upon detecting a transaction end event and finding a cache line of the transactional footprint having an expiration date older than or equal to a core observed time, an error is reported.

Testing a data coherency algorithm

Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.

Maintaining data order between buffers

Examples of techniques for tournament tree rollback for payload write exception are described herein. An aspect includes receiving a new record for a tournament sort. Another aspect includes determining a winner node of the tournament sort based on a tournament tree and the new record. Another aspect includes, based on determining the winner node of the tournament sort, writing out a payload of the winner node. Another aspect includes, in parallel with writing out the payload of the winner node, updating the tournament tree.

Tournament tree rollback for payload write exception

A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.

Cache management

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Schoenaich, Germany

Martin Recktenwald